[PATCH] D128286: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D128286#3605455 <https://reviews.llvm.org/D128286#3605455>, @craig.topper wrote:

> In D128286#3605390 <https://reviews.llvm.org/D128286#3605390>, @reames wrote:
>
>> Warning, I may be miss understanding the problem you're solving here, but...
>>
>> The case you mention appear to be specific to when VLEN=32 right?  If so, a cleaner way of phrasing the illegal cases would seem to be to compute the effective vector length after LMUL (i.e. VLEN/8 for mf8), and then disallow any case where the implied vector length is shorter than a single element of the element type.
>
> The problem is still valid for VLEN>=64 ELEN=32. While you are correct that a SEW=8 LMUL=1/8 would fit in a register for that config, there is no requirement in the spec for hardware to support it. The spec says that that the smallest fractional LMUL is SEWMIN/ELEN. Which would be 8/32 or 1/4 in this config. The spec goes on to say "For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive." So if ELEN is 32, LMUL=1/4 is only required to support SEW=8 and LMUL=1/2 is only required to support SEW=8 or 16.

I think I can still phrase that in the "does this fit" manner.  I just need to introduce a MINVLEN (which is simply ELEN), and ask whether an implied vector length for a given LMUL contains a least one element.


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