[llvm] 5fef62f - AMDGPU: Add missing implicit uses in tests
    Matt Arsenault via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Wed Jun 22 18:06:53 PDT 2022
    
    
  
Author: Matt Arsenault
Date: 2022-06-22T21:06:19-04:00
New Revision: 5fef62f6434fd2ff81af6345f1982a983978e208
URL: https://github.com/llvm/llvm-project/commit/5fef62f6434fd2ff81af6345f1982a983978e208
DIFF: https://github.com/llvm/llvm-project/commit/5fef62f6434fd2ff81af6345f1982a983978e208.diff
LOG: AMDGPU: Add missing implicit uses in tests
These tests were deleting the copy instruction, defeating
the purpose of having it.
Added: 
    
Modified: 
    llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
    llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
Removed: 
    
################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
index fd4e74568490..5f73958d5962 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
@@ -206,7 +206,7 @@ body:             |
 
   bb.2:
     $vgpr0 = COPY %1
-    S_ENDPGM 0
+    S_ENDPGM 0, implicit $vgpr0
 ...
 
 # GCN: name: negated_cond_vop2_used_vcc
diff  --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
index a9c8163f6e48..0fcc6680ce0d 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
@@ -231,7 +231,7 @@ body:             |
 
   bb.2:
     $vgpr0 = COPY %1
-    S_ENDPGM 0
+    S_ENDPGM 0, implicit $vgpr0
 ...
 
 # GCN: name: negated_cond_vop2_used_vcc
@@ -257,7 +257,7 @@ body:             |
     S_BRANCH %bb.2
 
   bb.2:
-    S_ENDPGM 0
+    S_ENDPGM 0, implicit $vgpr0
 ...
 
 # GCN: name: negated_cond_vop3_sel_wrong_subreg1
        
    
    
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