[llvm] 696169a - [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR.
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 21 16:14:25 PDT 2022
Author: Paul Walker
Date: 2022-06-22T00:11:24+01:00
New Revision: 696169a35d5cb656c205cabdcbf6524d6e2d1e8d
URL: https://github.com/llvm/llvm-project/commit/696169a35d5cb656c205cabdcbf6524d6e2d1e8d
DIFF: https://github.com/llvm/llvm-project/commit/696169a35d5cb656c205cabdcbf6524d6e2d1e8d.diff
LOG: [SVE] Add isel patterns that match "FpImm - A" to the immediate form of FSUBR.
Differential Revision: https://reviews.llvm.org/D128200
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 0ac5fc0ab2e5..648928a30f7d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -297,6 +297,9 @@ def AArch64fmls_p : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
[(AArch64fma_p node:$pred, (AArch64fneg_mt node:$pred, node:$op1, (undef)), node:$op2, node:$op3),
(AArch64fma_p node:$pred, node:$op2, (AArch64fneg_mt node:$pred, node:$op1, (undef)), node:$op3)]>;
+def AArch64fsubr_p : PatFrag<(ops node:$pg, node:$op1, node:$op2),
+ (AArch64fsub_p node:$pg, node:$op2, node:$op1)>;
+
def AArch64fneg_mt_nsz : PatFrag<(ops node:$pred, node:$op, node:$pt),
(AArch64fneg_mt node:$pred, node:$op, node:$pt), [{
return N->getFlags().hasNoSignedZeros();
@@ -460,11 +463,11 @@ let Predicates = [HasSVEorSME] in {
defm FMINNM_ZPmI : sve_fp_2op_i_p_zds<0b101, "fminnm", "FMINNM_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fminnm>;
defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", "FMAX_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmax>;
defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", "FMIN_ZPZI", sve_fpimm_zero_one, fpimm0, fpimm_one, int_aarch64_sve_fmin>;
-
+
defm FADD_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fadd_p>;
defm FSUB_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fsub_p>;
defm FMUL_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_two, fpimm_half, fpimm_two, AArch64fmul_p>;
- defm FSUBR_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one>;
+ defm FSUBR_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_half_one, fpimm_half, fpimm_one, AArch64fsubr_p>;
defm FMAXNM_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fmaxnm_p>;
defm FMINNM_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fminnm_p>;
defm FMAX_ZPZI : sve_fp_2op_i_p_zds_hfd<sve_fpimm_zero_one, fpimm0, fpimm_one, AArch64fmax_p>;
diff --git a/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll b/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll
index 8c688e626692..ef62ffd58bd5 100644
--- a/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll
@@ -1037,6 +1037,154 @@ define <vscale x 2 x double> @fsub_d_immone(<vscale x 2 x double> %a) #0 {
ret <vscale x 2 x double> %out
}
+;
+; FSUBR
+;
+
+define <vscale x 8 x half> @fsubr_h_immhalf(<vscale x 8 x half> %a) #0 {
+; CHECK-LABEL: fsubr_h_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+ %out = fsub <vscale x 8 x half> %splat, %a
+ ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsubr_h_immone(<vscale x 8 x half> %a) #0 {
+; CHECK-LABEL: fsubr_h_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+ %out = fsub <vscale x 8 x half> %splat, %a
+ ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x half> @fsubr_4h_immhalf(<vscale x 4 x half> %a) #0 {
+; CHECK-LABEL: fsubr_4h_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 4 x half> undef, half 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 4 x half> %elt, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+ %out = fsub <vscale x 4 x half> %splat, %a
+ ret <vscale x 4 x half> %out
+}
+
+define <vscale x 4 x half> @fsubr_4h_immone(<vscale x 4 x half> %a) #0 {
+; CHECK-LABEL: fsubr_4h_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 4 x half> undef, half 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 4 x half> %elt, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+ %out = fsub <vscale x 4 x half> %splat, %a
+ ret <vscale x 4 x half> %out
+}
+
+define <vscale x 2 x half> @fsubr_2h_immhalf(<vscale x 2 x half> %a) #0 {
+; CHECK-LABEL: fsubr_2h_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x half> undef, half 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x half> %elt, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x half> %splat, %a
+ ret <vscale x 2 x half> %out
+}
+
+define <vscale x 2 x half> @fsubr_2h_immone(<vscale x 2 x half> %a) #0 {
+; CHECK-LABEL: fsubr_2h_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x half> undef, half 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x half> %elt, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x half> %splat, %a
+ ret <vscale x 2 x half> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immhalf(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: fsubr_s_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+ %out = fsub <vscale x 4 x float> %splat, %a
+ ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immone(<vscale x 4 x float> %a) #0 {
+; CHECK-LABEL: fsubr_s_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+ %out = fsub <vscale x 4 x float> %splat, %a
+ ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x float> @fsubr_2s_immhalf(<vscale x 2 x float> %a) #0 {
+; CHECK-LABEL: fsubr_2s_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x float> undef, float 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x float> %elt, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x float> %splat, %a
+ ret <vscale x 2 x float> %out
+}
+
+define <vscale x 2 x float> @fsubr_2s_immone(<vscale x 2 x float> %a) #0 {
+; CHECK-LABEL: fsubr_2s_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x float> undef, float 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x float> %elt, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x float> %splat, %a
+ ret <vscale x 2 x float> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immhalf(<vscale x 2 x double> %a) #0 {
+; CHECK-LABEL: fsubr_d_immhalf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x double> %splat, %a
+ ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immone(<vscale x 2 x double> %a) #0 {
+; CHECK-LABEL: fsubr_d_immone:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+ %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+ %out = fsub <vscale x 2 x double> %splat, %a
+ ret <vscale x 2 x double> %out
+}
+
;; Arithmetic intrinsic declarations
declare <vscale x 8 x half> @llvm.maximum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)
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