[llvm] 4cbbb35 - AMDGPU: Regenerate test checks
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 21 12:37:20 PDT 2022
Author: Matt Arsenault
Date: 2022-06-21T15:37:12-04:00
New Revision: 4cbbb35fcbb6ff54274502956387494293d23d01
URL: https://github.com/llvm/llvm-project/commit/4cbbb35fcbb6ff54274502956387494293d23d01
DIFF: https://github.com/llvm/llvm-project/commit/4cbbb35fcbb6ff54274502956387494293d23d01.diff
LOG: AMDGPU: Regenerate test checks
Added:
Modified:
llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
index a54e829dea81..0093473964f1 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-loop-phi.mir
@@ -13,23 +13,27 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi
; CHECK: bb.0:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
- ; CHECK: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_BRANCH %bb.2
- ; CHECK: bb.1:
- ; CHECK: S_ENDPGM 0
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec
- ; CHECK: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
- ; CHECK: %1.sub1:vreg_64 = COPY %1.sub0
- ; CHECK: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store (s64), addrspace 3)
- ; CHECK: ATOMIC_FENCE 4, 2
- ; CHECK: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
- ; CHECK: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
- ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
- ; CHECK: S_BRANCH %bb.2
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
+ ; CHECK-NEXT: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec
+ ; CHECK-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: %1.sub1:vreg_64 = COPY %1.sub0
+ ; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store (s64), addrspace 3)
+ ; CHECK-NEXT: ATOMIC_FENCE 4, 2
+ ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
+ ; CHECK-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.2
bb.0:
successors: %bb.2
@@ -62,21 +66,25 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_reorder
; CHECK: bb.0:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
- ; CHECK: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_BRANCH %bb.2
- ; CHECK: bb.1:
- ; CHECK: S_ENDPGM 0
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: %1.sub1:vreg_64 = COPY %1.sub0
- ; CHECK: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store (s64), addrspace 3)
- ; CHECK: ATOMIC_FENCE 4, 2
- ; CHECK: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc
- ; CHECK: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
- ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
- ; CHECK: S_BRANCH %bb.2
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
+ ; CHECK-NEXT: undef %1.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %1.sub1:vreg_64 = COPY %1.sub0
+ ; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %3:vgpr_32, %1, 0, 0, implicit $exec :: (store (s64), addrspace 3)
+ ; CHECK-NEXT: ATOMIC_FENCE 4, 2
+ ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc
+ ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.2
bb.0:
successors: %bb.2
@@ -108,24 +116,28 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi_physreg
; CHECK: bb.0:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 -1
- ; CHECK: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_BRANCH %bb.2
- ; CHECK: bb.1:
- ; CHECK: S_ENDPGM 0
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $sgpr4_sgpr5
- ; CHECK: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec
- ; CHECK: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
- ; CHECK: %0.sub1:vreg_64 = COPY %0.sub0
- ; CHECK: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store (s64), addrspace 3)
- ; CHECK: ATOMIC_FENCE 4, 2
- ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 0
- ; CHECK: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
- ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
- ; CHECK: S_BRANCH %bb.2
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 -1
+ ; CHECK-NEXT: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec
+ ; CHECK-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
+ ; CHECK-NEXT: %0.sub1:vreg_64 = COPY %0.sub0
+ ; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store (s64), addrspace 3)
+ ; CHECK-NEXT: ATOMIC_FENCE 4, 2
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 0
+ ; CHECK-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.2
bb.0:
successors: %bb.2
@@ -158,22 +170,26 @@ tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_physreg_reorder
; CHECK: bb.0:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 -1
- ; CHECK: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_BRANCH %bb.2
- ; CHECK: bb.1:
- ; CHECK: S_ENDPGM 0
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $sgpr4_sgpr5
- ; CHECK: %0.sub1:vreg_64 = COPY %0.sub0
- ; CHECK: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store (s64), addrspace 3)
- ; CHECK: ATOMIC_FENCE 4, 2
- ; CHECK: $vcc = S_ANDN2_B64 $exec, $sgpr4_sgpr5, implicit-def dead $scc
- ; CHECK: $sgpr4_sgpr5 = S_MOV_B64 0
- ; CHECK: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
- ; CHECK: S_BRANCH %bb.2
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 -1
+ ; CHECK-NEXT: undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %0.sub1:vreg_64 = COPY %0.sub0
+ ; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %2:vgpr_32, %0, 0, 0, implicit $exec :: (store (s64), addrspace 3)
+ ; CHECK-NEXT: ATOMIC_FENCE 4, 2
+ ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, $sgpr4_sgpr5, implicit-def dead $scc
+ ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 0
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.2
bb.0:
successors: %bb.2
diff --git a/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir b/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
index c60d8297f57d..71290075e75e 100644
--- a/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/undef-subreg-use-after-coalesce.mir
@@ -13,8 +13,8 @@ body: |
bb.0:
; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_0
; CHECK: undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: dead %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_ENDPGM 0, implicit undef %0.sub2
+ ; CHECK-NEXT: dead %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit undef %0.sub2
undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
%0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
%1:vreg_96 = COPY killed %0
@@ -31,8 +31,8 @@ body: |
bb.0:
; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_composed
; CHECK: undef %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: dead %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK: S_ENDPGM 0, implicit undef %2.sub1:vreg_64
+ ; CHECK-NEXT: dead %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit undef %2.sub1:vreg_64
undef %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
%0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
%1:vreg_128 = COPY killed %0
@@ -64,11 +64,12 @@ body: |
; CHECK-LABEL: name: undef_subreg_use_after_full_copy_coalesce_1
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
- ; CHECK: undef %2.sub0:vreg_96 = COPY $vgpr0
- ; CHECK: %2.sub1:vreg_96 = COPY $vgpr1
- ; CHECK: S_NOP 0, implicit undef %2.sub2
- ; CHECK: S_NOP 0, implicit %2.sub1
- ; CHECK: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: undef %2.sub0:vreg_96 = COPY $vgpr0
+ ; CHECK-NEXT: %2.sub1:vreg_96 = COPY $vgpr1
+ ; CHECK-NEXT: S_NOP 0, implicit undef %2.sub2
+ ; CHECK-NEXT: S_NOP 0, implicit %2.sub1
+ ; CHECK-NEXT: S_ENDPGM 0
%0:vgpr_32 = COPY killed $vgpr0
%1:vgpr_32 = COPY killed $vgpr1
undef %2.sub0:vreg_96 = COPY killed %0
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