[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1262
+      // spill and restore them even if they are marked Caller-saved.
+      if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32)
+        MFI->addToLaneVGPRs(MF, MI.getOperand(0).getReg());
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@nhaehnle the general use of writelane (writelane intrinsic) currently being considered for spilling is due to the fact that we identify all writelane instructions at this point.
This is a pre-patch for spilling SGPRs to virtual VGPRs during `SILowerSGPRSpills` pass (D124196). Once we spill SGPRs to virtVGPRs, we don't know the actual VGPRs they get until RA. To identify the actual VGPRs used for SGPR spills, we have no choice other than walking through all BBs at a later stage.  At this point, we don't have a better way to distinguish the writelane instructions for spills from the general use.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192