[PATCH] D128283: [AArch64][SVE] Support optimized lowered selection with small SVE bits

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Hi @Allen, typically the SVE intrinsics only support legal types.  This is a conscience choice because otherwise it will be very difficult to offer universal type support for all these target specific operations (i.e. where would we draw the line).  Is there a reason not to use `llvm.vector.reduce.and` instead?


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  https://reviews.llvm.org/D128283/new/

https://reviews.llvm.org/D128283