[llvm] 3f81841 - [AArch64] Add Extract(DUP(C)) as a canonical constant.

[David Green via llvm-commits]

Author: David Green
Date: 2022-06-21T09:51:22+01:00
New Revision: 3f81841474fefcf10fea0ed7fc21f47af3c7b80a

URL: https://github.com/llvm/llvm-project/commit/3f81841474fefcf10fea0ed7fc21f47af3c7b80a
DIFF: https://github.com/llvm/llvm-project/commit/3f81841474fefcf10fea0ed7fc21f47af3c7b80a.diff

LOG: [AArch64] Add Extract(DUP(C)) as a canonical constant.

As a followup to D128144, this adds extract(DUP(C)) as a canonical
constant to prevent it being transformed back into a BUILD_VECTOR,
leading to an infinite loop.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/lib/Target/AArch64/AArch64ISelLowering.h
    llvm/test/CodeGen/AArch64/arm64-dup.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index bec4d7919aac8..c48244e78ad5a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21408,6 +21408,13 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
       Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
 }
 
+bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
+  return Op.getOpcode() == AArch64ISD::DUP ||
+         (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
+          Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
+         TargetLowering::isTargetCanonicalConstantNode(Op);
+}
+
 bool AArch64TargetLowering::isConstantUnsignedBitfieldExtractLegal(
     unsigned Opc, LLT Ty1, LLT Ty2) const {
   return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 4c64684cbcd85..126eaa741a0f3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1129,10 +1129,7 @@ class AArch64TargetLowering : public TargetLowering {
                                          TargetLoweringOpt &TLO,
                                          unsigned Depth) const override;
 
-  bool isTargetCanonicalConstantNode(SDValue Op) const override {
-    return Op.getOpcode() == AArch64ISD::DUP ||
-           TargetLowering::isTargetCanonicalConstantNode(Op);
-  }
+  bool isTargetCanonicalConstantNode(SDValue Op) const override;
 
   // Normally SVE is only used for byte size vectors that do not fit within a
   // NEON vector. This changes when OverrideNEON is true, allowing SVE to be

diff  --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll
index 840fd0fc7d9a1..241ff1254a11f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dup.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll
@@ -460,3 +460,47 @@ define void @disguised_dup(<4 x float> %x, <4 x float>* %p1, <4 x float>* %p2) {
   store <4 x float> %dup, <4 x float>* %p2, align 8
   ret void
 }
+
+define <2 x i32> @dup_const2(<2 x i32> %A) nounwind {
+; CHECK-LABEL: dup_const2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #32770
+; CHECK-NEXT:    movk w8, #128, lsl #16
+; CHECK-NEXT:    dup.2s v1, w8
+; CHECK-NEXT:    add.2s v0, v0, v1
+; CHECK-NEXT:    ret
+  %tmp2 = add <2 x i32> %A, <i32 8421378, i32 8421378>
+  ret <2 x i32> %tmp2
+}
+
+define <2 x i32> @dup_const4_ext(<4 x i32> %A) nounwind {
+; CHECK-LABEL: dup_const4_ext:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #32769
+; CHECK-NEXT:    movk w8, #128, lsl #16
+; CHECK-NEXT:    dup.2s v1, w8
+; CHECK-NEXT:    add.2s v0, v0, v1
+; CHECK-NEXT:    ret
+  %tmp1 = add <4 x i32> %A, <i32 8421377, i32 8421377, i32 8421377, i32 8421377>
+  %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @dup_const24(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: dup_const24:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #32768
+; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT:    movk w8, #128, lsl #16
+; CHECK-NEXT:    dup.4s v3, w8
+; CHECK-NEXT:    add.2s v0, v0, v3
+; CHECK-NEXT:    mov.d v0[1], v1[0]
+; CHECK-NEXT:    add.4s v1, v2, v3
+; CHECK-NEXT:    eor.16b v0, v1, v0
+; CHECK-NEXT:    ret
+  %tmp1 = add <2 x i32> %A, <i32 8421376, i32 8421376>
+  %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %tmp3 = add <4 x i32> %C, <i32 8421376, i32 8421376, i32 8421376, i32 8421376>
+  %tmp5 = xor <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}