[llvm] 0198448 - Revert "[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE"

[Amir Ayupov via llvm-commits]

Author: Amir Ayupov
Date: 2022-06-20T12:42:08-07:00
New Revision: 0198448a4b91886fc3883a91a09dd9d7e87ce4ef

URL: https://github.com/llvm/llvm-project/commit/0198448a4b91886fc3883a91a09dd9d7e87ce4ef
DIFF: https://github.com/llvm/llvm-project/commit/0198448a4b91886fc3883a91a09dd9d7e87ce4ef.diff

LOG: Revert "[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE"

This reverts commit 4cd416193cc126355a22b2c9e5c1df3a49b59e50.

Added: 
    

Modified: 
    llvm/test/TableGen/get-operand-type.td
    llvm/utils/TableGen/InstrInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/get-operand-type.td b/llvm/test/TableGen/get-operand-type.td
index 905adfad30eb5..27607f57a8d48 100644
--- a/llvm/test/TableGen/get-operand-type.td
+++ b/llvm/test/TableGen/get-operand-type.td
@@ -46,10 +46,7 @@ def InstC : Instruction {
 }
 
 // CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
-// CHECK:        /* InstA */
-// CHECK-NEXT:   OpA, OpB, i32imm,
-// CHECK-NEXT:   /* InstB */
-// CHECK-NEXT:   i32imm, -1,
-// CHECK-NEXT:   /* InstC */
-// CHECK-NEXT:   RegClass, RegOp,
+// CHECK:        OpTypes::OpA, OpTypes::OpB, OpTypes::i32imm,
+// CHECK-NEXT:   OpTypes::i32imm, -1,
+// CHECK-NEXT:   OpTypes::RegClass, OpTypes::RegOp,
 // CHECK: #endif // GET_INSTRINFO_OPERAND_TYPE

diff  --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index e33843b0c06a2..56252f0b69ccb 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -379,9 +379,6 @@ void InstrInfoEmitter::emitOperandTypeMappings(
   OS << "namespace " << Namespace << " {\n";
   OS << "LLVM_READONLY\n";
   OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
-  auto getInstrName = [&](int I) -> StringRef {
-    return NumberedInstructions[I]->TheDef->getName();
-  };
   // TODO: Factor out duplicate operand lists to compress the tables.
   if (!NumberedInstructions.empty()) {
     std::vector<int> OperandOffsets;
@@ -411,10 +408,8 @@ void InstrInfoEmitter::emitOperandTypeMappings(
     OS << ((OperandRecords.size() <= UINT16_MAX) ? "  const uint16_t"
                                                  : "  const uint32_t");
     OS << " Offsets[] = {\n";
-    for (int I = 0, E = OperandOffsets.size(); I != E; ++I) {
-      OS << "    /* " << getInstrName(I) << " */\n";
+    for (int I = 0, E = OperandOffsets.size(); I != E; ++I)
       OS << "    " << OperandOffsets[I] << ",\n";
-    }
     OS << "  };\n";
 
     // Add an entry for the end so that we don't need to special case it below.
@@ -424,22 +419,22 @@ void InstrInfoEmitter::emitOperandTypeMappings(
     // Size the signed integer operand type to save space.
     assert(EnumVal <= INT16_MAX &&
            "Too many operand types for operand types table");
-    OS << "\n  using namespace OpTypes;\n";
     OS << ((EnumVal <= INT8_MAX) ? "  const int8_t" : "  const int16_t");
     OS << " OpcodeOperandTypes[] = {\n    ";
-    for (int I = 0, E = OperandRecords.size(), CurOffset = 0; I != E; ++I) {
+    for (int I = 0, E = OperandRecords.size(), CurOffset = 1; I != E; ++I) {
       // We print each Opcode's operands in its own row.
       if (I == OperandOffsets[CurOffset]) {
-        OS << "\n    /* " << getInstrName(CurOffset) << " */\n    ";
+        OS << "\n    ";
+        // If there are empty rows, mark them with an empty comment.
         while (OperandOffsets[++CurOffset] == I)
-          OS << "/* " << getInstrName(CurOffset) << " */\n    ";
+          OS << "/**/\n    ";
       }
       Record *OpR = OperandRecords[I];
       if ((OpR->isSubClassOf("Operand") ||
            OpR->isSubClassOf("RegisterOperand") ||
            OpR->isSubClassOf("RegisterClass")) &&
           !OpR->isAnonymous())
-        OS << OpR->getName();
+        OS << "OpTypes::" << OpR->getName();
       else
         OS << -1;
       OS << ", ";