[llvm] 1484709 - [RISCV] Delete unexercised VL=0 vsetvli compatibility logic

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-06-20T10:15:31-07:00
New Revision: 14847098f90b291e847d283fe985d5f15b49ffe3

URL: https://github.com/llvm/llvm-project/commit/14847098f90b291e847d283fe985d5f15b49ffe3
DIFF: https://github.com/llvm/llvm-project/commit/14847098f90b291e847d283fe985d5f15b49ffe3.diff

LOG: [RISCV] Delete unexercised VL=0 vsetvli compatibility logic

The code being removed is technically correct; if we end up with two VL=0 instructions next to each other, we can avoid a state transition if the second is a scalar move.  However, since both ops are also nops, we should simply delete them instead.  As such, this compatibility rule simply complicates the code for no purpose.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index ea7c18db4391..127e88dcaa14 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -502,11 +502,6 @@ class VSETVLIInfo {
   unsigned getSEW() const { return SEW; }
   RISCVII::VLMUL getVLMUL() const { return VLMul; }
 
-  bool hasZeroAVL() const {
-    if (hasAVLImm())
-      return getAVLImm() == 0;
-    return false;
-  }
   bool hasNonZeroAVL() const {
     if (hasAVLImm())
       return getAVLImm() > 0;
@@ -996,13 +991,12 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
     return false;
 
   // For vmv.s.x and vfmv.s.f, there is only two behaviors, VL = 0 and VL > 0.
-  // So it's compatible when we could make sure that both VL be the same
-  // situation.  Additionally, if writing to an implicit_def operand, we
-  // don't need to preserve any other bits and are thus compatible with any
-  // larger etype, and can disregard policy bits.
+  // VL=0 is uninteresting (as it should have been deleted already), so it is
+  // compatible if we can prove both are non-zero.  Additionally, if writing
+  // to an implicit_def operand, we don't need to preserve any other bits and
+  // are thus compatible with any larger etype, and can disregard policy bits.
   if (isScalarMoveInstr(MI) &&
-      ((CurInfo.hasNonZeroAVL() && Require.hasNonZeroAVL()) ||
-       (CurInfo.hasZeroAVL() && Require.hasZeroAVL()))) {
+      CurInfo.hasNonZeroAVL() && Require.hasNonZeroAVL()) {
     auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
     if (VRegDef && VRegDef->isImplicitDef() &&
         CurInfo.getSEW() >= Require.getSEW())
@@ -1057,8 +1051,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, const MachineInstr &M
   // prevent extending live range of an avl register operand.
   // TODO: We can probably relax this for immediates.
   if (isScalarMoveInstr(MI) && PrevInfo.isValid() &&
-      ((PrevInfo.hasNonZeroAVL() && Info.hasNonZeroAVL()) ||
-       (PrevInfo.hasZeroAVL() && Info.hasZeroAVL())) &&
+      PrevInfo.hasNonZeroAVL() && Info.hasNonZeroAVL() &&
       Info.hasSameVLMAX(PrevInfo)) {
     if (PrevInfo.hasAVLImm())
       Info.setAVLImm(PrevInfo.getAVLImm());