[PATCH] D88569: [DAGCombiner] Call SimplifyDemandedBits to simplify EXTRACT_VECTOR_ELT

[Jay Foad via Phabricator via llvm-commits]

foad updated this revision to Diff 438396.
foad added a comment.
Herald added subscribers: armkevincheng, eric-k256.
Herald added a reviewer: sjarus.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88569/new/

https://reviews.llvm.org/D88569

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/arm64-build-vector.ll
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
  llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
  llvm/test/CodeGen/AMDGPU/load-global-i16.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/usubsat.ll
  llvm/test/CodeGen/ARM/aes-erratum-fix.ll
  llvm/test/CodeGen/ARM/fp16-insert-extract.ll
  llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
  llvm/test/CodeGen/ARM/vdup.ll
  llvm/test/CodeGen/ARM/vldlane.ll
  llvm/test/CodeGen/ARM/vzip.ll
  llvm/test/CodeGen/Mips/cconv/vector.ll
  llvm/test/CodeGen/PowerPC/pr45709.ll
  llvm/test/CodeGen/SystemZ/memset-08.ll
  llvm/test/CodeGen/SystemZ/store-replicated-vals.ll
  llvm/test/CodeGen/Thumb2/active_lane_mask.ll
  llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
  llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
  llvm/test/CodeGen/Thumb2/mve-vabdus.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
  llvm/test/CodeGen/Thumb2/mve-vld2.ll
  llvm/test/CodeGen/Thumb2/mve-vld3.ll
  llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
  llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
  llvm/test/CodeGen/Thumb2/mve-vst2.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
  llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
  llvm/test/CodeGen/X86/2012-07-10-extload64.ll
  llvm/test/CodeGen/X86/bitcast-vector-bool.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/combine-concatvectors.ll
  llvm/test/CodeGen/X86/fold-load-vec.ll
  llvm/test/CodeGen/X86/half.ll
  llvm/test/CodeGen/X86/madd.ll
  llvm/test/CodeGen/X86/nontemporal-3.ll
  llvm/test/CodeGen/X86/pr41619.ll
  llvm/test/CodeGen/X86/promote-cmp.ll
  llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/X86/vec_setcc.ll
  llvm/test/CodeGen/X86/vec_zero_cse.ll
  llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vselect-constants.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/widen_cast-5.ll
  llvm/test/CodeGen/X86/widen_shuffle-1.ll