[llvm] ba30621 - [AMDGPU] Reorder cases. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-06-20T14:30:17+01:00
New Revision: ba306216d2806d17a6fb08b6e9c02c30a0999380

URL: https://github.com/llvm/llvm-project/commit/ba306216d2806d17a6fb08b6e9c02c30a0999380
DIFF: https://github.com/llvm/llvm-project/commit/ba306216d2806d17a6fb08b6e9c02c30a0999380.diff

LOG: [AMDGPU] Reorder cases. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 79fdae5bcee3..4256fc8f4f9e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3123,16 +3123,16 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
       constrainOpWithReadfirstlane(MI, MRI, 2);
       return;
     }
-    case Intrinsic::amdgcn_exp_row:
-      applyDefaultMapping(OpdMapper);
-      constrainOpWithReadfirstlane(MI, MRI, 8); // M0
-      return;
     case Intrinsic::amdgcn_lds_direct_load: {
       applyDefaultMapping(OpdMapper);
       // Readlane for m0 value, which is always the last operand.
       constrainOpWithReadfirstlane(MI, MRI, MI.getNumOperands() - 1); // Index
       return;
     }
+    case Intrinsic::amdgcn_exp_row:
+      applyDefaultMapping(OpdMapper);
+      constrainOpWithReadfirstlane(MI, MRI, 8); // M0
+      return;
     default: {
       if (const AMDGPU::RsrcIntrinsic *RSrcIntrin =
               AMDGPU::lookupRsrcIntrinsic(IntrID)) {