[PATCH] D128189: [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd7762a3b369e: [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11 (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128189/new/

https://reviews.llvm.org/D128189

Files:
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
  llvm/test/CodeGen/AMDGPU/s_code_end.ll


Index: llvm/test/CodeGen/AMDGPU/s_code_end.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/s_code_end.ll
+++ llvm/test/CodeGen/AMDGPU/s_code_end.ll
@@ -41,10 +41,10 @@
 ; GCN-ASM-NEXT:   [[END_LABEL3:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_function, [[END_LABEL3]]-a_function
 ; GFX10END-ASM:           .p2alignl 6, 3214868480
-; GFX11END-ASM:           .p2alignl 6, 3214868480
+; GFX11END-ASM:           .p2alignl 7, 3214868480
 ; GFX90AEND-ASM:          .p2alignl 6, 3212836864
 ; GFX10END-ASM-NEXT:      .fill 48, 4, 3214868480
-; GFX11END-ASM-NEXT:      .fill 48, 4, 3214868480
+; GFX11END-ASM-NEXT:      .fill 96, 4, 3214868480
 ; GFX90AEND-ASM-NEXT:     .fill 256, 4, 3212836864
 ; GFX10NOEND-NOT:         .fill
 ; GFX11NOEND-NOT:         .fill
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -301,7 +301,7 @@
   uint32_t Encoded_pad = Encoded_s_code_end;
 
   // Instruction cache line size in bytes.
-  const unsigned Log2CacheLineSize = 6;
+  const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
   const unsigned CacheLineSize = 1u << Log2CacheLineSize;
 
   // Extra padding amount in bytes to support prefetch mode 3.
@@ -824,7 +824,7 @@
   uint32_t Encoded_pad = Encoded_s_code_end;
 
   // Instruction cache line size in bytes.
-  const unsigned Log2CacheLineSize = 6;
+  const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
   const unsigned CacheLineSize = 1u << Log2CacheLineSize;
 
   // Extra padding amount in bytes to support prefetch mode 3.


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