[PATCH] D128187: [RISCV] Add ADDI instr for computing FrameIndex address
luxufan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 20 05:30:29 PDT 2022
StephenFan created this revision.
StephenFan added reviewers: frasercrmck, craig.topper, reames, jacquesguan, luismarques.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
StephenFan requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
RVV doesn't have immediate field for memory addressing. Currently
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.
This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as `ADDI GPR, targetframeindex`.
There are 2 advantages for such change:
1. Stack objects address computing can be optimized by machine function
passes.
2. Since the ADDI instruction's destination register can be used as a
temp register, we can save an emergency spill slot.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128187
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
llvm/test/CodeGen/RISCV/rvv/memory-args.ll
llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
llvm/test/CodeGen/RISCV/rvv/stepvector.ll
llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
llvm/test/CodeGen/RISCV/rvv/vaadd.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vadd.ll
llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/vasub.ll
llvm/test/CodeGen/RISCV/rvv/vasubu.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmul.ll
llvm/test/CodeGen/RISCV/rvv/vmulh.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vrsub.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/vsub.ll
llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
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