[PATCH] D128185: [AMDGPU] Set GFX11 null export target based on export attributes
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 20 05:09:03 PDT 2022
foad created this revision.
foad added reviewers: Joe_Nash, rampitec, piotr, critson, ruiling.
Herald added subscribers: kosarev, jsilvanus, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
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foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
If shader only has depth exports use MRTZ otherwise use MRT0.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128185
Files:
llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
llvm/test/CodeGen/AMDGPU/early-term.mir
Index: llvm/test/CodeGen/AMDGPU/early-term.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/early-term.mir
+++ llvm/test/CodeGen/AMDGPU/early-term.mir
@@ -26,7 +26,12 @@
ret void
}
+ define amdgpu_ps void @early_term_depth_only() #1 {
+ ret void
+ }
+
attributes #0 = { "amdgpu-color-export"="0" "amdgpu-depth-export"="0" }
+ attributes #1 = { "amdgpu-color-export"="0" "amdgpu-depth-export"="1" }
...
---
@@ -255,3 +260,41 @@
EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
S_ENDPGM 0
...
+
+---
+name: early_term_depth_only
+tracksRegLiveness: true
+liveins:
+ - { reg: '$sgpr0' }
+ - { reg: '$sgpr1' }
+body: |
+ ; GCN-LABEL: name: early_term_depth_only
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x80000000), %bb.2(0x00000000)
+ ; GCN: liveins: $sgpr0, $sgpr1
+ ; GCN: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ ; GCN: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: bb.1:
+ ; GCN: liveins: $vgpr0
+ ; GCN: EXP_DONE 8, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
+ ; GCN: S_ENDPGM 0
+ ; GCN: bb.2:
+ ; GCN: $exec = S_MOV_B64 0
+ ; GFX9: EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
+ ; GFX10: EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
+ ; GFX11: EXP_DONE 8, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ successors: %bb.1
+
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+ dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc
+ SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
+
+ bb.1:
+ liveins: $vgpr0
+ EXP_DONE 8, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
+ S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
+++ llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
@@ -72,16 +72,22 @@
bool IsPS = F.getCallingConv() == CallingConv::AMDGPU_PS;
// Check if hardware has been configured to expect color or depth exports.
- bool HasExports =
- AMDGPU::getHasColorExport(F) || AMDGPU::getHasDepthExport(F);
+ bool HasColorExports = AMDGPU::getHasColorExport(F);
+ bool HasDepthExports = AMDGPU::getHasDepthExport(F);
+ bool HasExports = HasColorExports || HasDepthExports;
// Prior to GFX10, hardware always expects at least one export for PS.
bool MustExport = !AMDGPU::isGFX10Plus(TII->getSubtarget());
if (IsPS && (HasExports || MustExport)) {
// Generate "null export" if hardware is expecting PS to export.
+ const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>();
+ int Target =
+ ST.hasNullExportTarget()
+ ? AMDGPU::Exp::ET_NULL
+ : (HasColorExports ? AMDGPU::Exp::ET_MRT0 : AMDGPU::Exp::ET_MRTZ);
BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE))
- .addImm(AMDGPU::Exp::ET_NULL)
+ .addImm(Target)
.addReg(AMDGPU::VGPR0, RegState::Undef)
.addReg(AMDGPU::VGPR0, RegState::Undef)
.addReg(AMDGPU::VGPR0, RegState::Undef)
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