[PATCH] D127603: [AArch64] isSeveralBitsExtractOpFromShr - match UBFM patterns with value tracking (RFC)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon abandoned this revision.
RKSimon added a comment.

D125836 <https://reviews.llvm.org/D125836> tweaks AArch64TargetLowering::shouldFoldConstantShiftPairToMask to ensure we don't mess with srl(shl(x,c1),c2) if it matches a UBFX pattern.

Abandoning this for now, but we could revive this in the future if it ever becomes useful (I also noticed that ARM has some similar matching). Bit extraction instructions are common enough that a generic opcode could even be considered....


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127603/new/

https://reviews.llvm.org/D127603