[PATCH] D126652: [RISCV] Change GPRPF64's hwmode and spill alignment

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

I'm a little nervous something may subtly break here (e.g. due to an assumption that any spilled f64 value will always be stored properly aligned). I note AFGR64 on Mips and IntPair on Sparc for instance both have 64-bit alignment. That's just a gut feeling though - I don't have a particular broken test case in mind. Have you explored this kind of potential problem?


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  https://reviews.llvm.org/D126652/new/

https://reviews.llvm.org/D126652