[llvm] 76f6093 - [ARM] Allow distributing postinc with PHI uses

[David Green via llvm-commits]

Author: David Green
Date: 2022-06-20T10:08:21+01:00
New Revision: 76f60931e2acedfe69aef614b07f902fbc814838

URL: https://github.com/llvm/llvm-project/commit/76f60931e2acedfe69aef614b07f902fbc814838
DIFF: https://github.com/llvm/llvm-project/commit/76f60931e2acedfe69aef614b07f902fbc814838.diff

LOG: [ARM] Allow distributing postinc with PHI uses

Although this doesn't usually come up, we can have uses of the
BaseAccess of a distributed postinc being a PHI. This doesn't need the
usual dominance check as we will dominate along the phi edge, allowing
us to still create a postinc load/store.

Differential Revision: https://reviews.llvm.org/D127676

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index fb9d6863aca74..0a38f5633ae3b 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2896,10 +2896,12 @@ bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) {
     LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on VirtualReg "
                       << Base.virtRegIndex() << "\n");
 
-    // Make sure that Increment has no uses before BaseAccess.
+    // Make sure that Increment has no uses before BaseAccess that are not PHI
+    // uses.
     for (MachineInstr &Use :
         MRI->use_nodbg_instructions(Increment->getOperand(0).getReg())) {
-      if (!DT->dominates(BaseAccess, &Use) || &Use == BaseAccess) {
+      if (&Use == BaseAccess || (Use.getOpcode() != TargetOpcode::PHI &&
+                                 !DT->dominates(BaseAccess, &Use))) {
         LLVM_DEBUG(dbgs() << "  BaseAccess doesn't dominate use of increment\n");
         return false;
       }

diff  --git a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
index 3e1ff87915a0c..f53c3e7476616 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
@@ -25,11 +25,11 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
 ; CHECK-NEXT:    vldrh.u16 q5, [r1], #32
 ; CHECK-NEXT:    mov r4, r5
 ; CHECK-NEXT:    movs r7, #0
-; CHECK-NEXT:    vldrh.u16 q1, [r0, #-16]
+; CHECK-NEXT:    vldrh.u16 q2, [r0, #-16]
 ; CHECK-NEXT:    mov r6, r5
 ; CHECK-NEXT:    sub.w lr, lr, #1
 ; CHECK-NEXT:    vldrh.u16 q3, [r1, #-16]
-; CHECK-NEXT:    vldrh.u16 q2, [r1], #32
+; CHECK-NEXT:    vldrh.u16 q1, [r1], #32
 ; CHECK-NEXT:    vldrh.u16 q0, [r0], #32
 ; CHECK-NEXT:    vmlsldava.s16 r4, r7, q4, q5
 ; CHECK-NEXT:    cmp.w lr, #0
@@ -38,36 +38,35 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  .LBB0_2: @ %while.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q1, q3
-; CHECK-NEXT:    vmlsldava.s16 r4, r7, q1, q3
-; CHECK-NEXT:    vldrh.u16 q1, [r0, #-16]
-; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q0, q2
-; CHECK-NEXT:    vmlsldava.s16 r4, r7, q0, q2
+; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q2, q3
+; CHECK-NEXT:    vmlsldava.s16 r4, r7, q2, q3
+; CHECK-NEXT:    vldrh.u16 q2, [r0, #-16]
+; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q0, q1
+; CHECK-NEXT:    vmlsldava.s16 r4, r7, q0, q1
 ; CHECK-NEXT:    vldrh.u16 q0, [r0], #32
 ; CHECK-NEXT:    vldrh.u16 q3, [r1, #-16]
-; CHECK-NEXT:    vldrh.u16 q2, [r1]
-; CHECK-NEXT:    adds r1, #32
+; CHECK-NEXT:    vldrh.u16 q1, [r1], #32
 ; CHECK-NEXT:    le lr, .LBB0_2
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    mov.w lr, #14
-; CHECK-NEXT:    vmlsldava.s16 r4, r7, q1, q3
-; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q1, q3
+; CHECK-NEXT:    vmlsldava.s16 r4, r7, q2, q3
+; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q2, q3
 ; CHECK-NEXT:    and.w r2, lr, r2, lsl #1
-; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q0, q2
-; CHECK-NEXT:    vldrh.u16 q1, [r0, #-16]
-; CHECK-NEXT:    vmlsldava.s16 r4, r7, q0, q2
+; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q0, q1
+; CHECK-NEXT:    vldrh.u16 q2, [r0, #-16]
+; CHECK-NEXT:    vmlsldava.s16 r4, r7, q0, q1
 ; CHECK-NEXT:    vldrh.u16 q0, [r1, #-16]
 ; CHECK-NEXT:    vctp.16 r2
 ; CHECK-NEXT:    vpstt
-; CHECK-NEXT:    vldrht.u16 q2, [r0]
+; CHECK-NEXT:    vldrht.u16 q1, [r0]
 ; CHECK-NEXT:    vldrht.u16 q3, [r1]
-; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q1, q0
-; CHECK-NEXT:    vmlsldava.s16 r4, r7, q1, q0
+; CHECK-NEXT:    vmlaldavax.s16 r6, r5, q2, q0
+; CHECK-NEXT:    vmlsldava.s16 r4, r7, q2, q0
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlsldavat.s16 r4, r7, q2, q3
+; CHECK-NEXT:    vmlsldavat.s16 r4, r7, q1, q3
 ; CHECK-NEXT:    cmp r2, #9
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlaldavaxt.s16 r6, r5, q2, q3
+; CHECK-NEXT:    vmlaldavaxt.s16 r6, r5, q1, q3
 ; CHECK-NEXT:    blo .LBB0_10
 ; CHECK-NEXT:  @ %bb.4: @ %do.body.1
 ; CHECK-NEXT:    subs r2, #8