[PATCH] D128159: [DAG] Enable scalable vectors handling in computeKnownBits

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: RKSimon, craig.topper, paulwalker-arm, david-arm, efriedma.
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The computeKnownBits functions do not currently handle known bits of scalable vectors, as the meaning of DemandedElts is unclear for a vector that is scalable. This changes that so that the majority of knownBits is run, with the check for scalable vectors being pushed into the individual cases that a not trivially lane-wise.  The DemandedElts size is set to getVectorMinNumElements, although this patch doesn't make a strong opinion as to what that means, exactly. It could be the common demanded elements from any vscale repetitions of the operation, but nothing currently makes use of it in that way.

In order to keep the tests working this also:

- Adds known bits for ISD::SPLAT_VECTOR, which is the same bits as the input element (possibly truncated).
- Adds some simple known bits for ISD::STEP_VECTOR, which for power-two increments we know lower bit zeroes.
- The patterns for INDEX were made to work with adds or add-like-ors, to keep them working as intended.


https://reviews.llvm.org/D128159

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-knownbits.ll
  llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
  llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

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