[llvm] 362814d - [InstCombine] Update icmp-and-shift check-next name; NFC

[via llvm-commits]

Author: chenglin.bi
Date: 2022-06-20T11:49:16+08:00
New Revision: 362814d2247ed0d5d384f856e23f0d98d4c3b0af

URL: https://github.com/llvm/llvm-project/commit/362814d2247ed0d5d384f856e23f0d98d4c3b0af
DIFF: https://github.com/llvm/llvm-project/commit/362814d2247ed0d5d384f856e23f0d98d4c3b0af.diff

LOG: [InstCombine] Update icmp-and-shift check-next name; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/icmp-and-shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/icmp-and-shift.ll b/llvm/test/Transforms/InstCombine/icmp-and-shift.ll
index a67017fb8159..ae77e74bb220 100644
--- a/llvm/test/Transforms/InstCombine/icmp-and-shift.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-and-shift.ll
@@ -5,8 +5,8 @@ declare void @use(i8)
 
 define i32 @icmp_eq_and_pow2_shl1(i32 %0) {
 ; CHECK-LABEL: @icmp_eq_and_pow2_shl1(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[TMP0:%.*]], 4
-; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP0:%.*]], 4
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %shl = shl i32 1, %0
@@ -18,8 +18,8 @@ define i32 @icmp_eq_and_pow2_shl1(i32 %0) {
 
 define <2 x i32> @icmp_eq_and_pow2_shl1_vec(<2 x i32> %0) {
 ; CHECK-LABEL: @icmp_eq_and_pow2_shl1_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <2 x i32> [[TMP0:%.*]], <i32 4, i32 4>
-; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP0:%.*]], <i32 4, i32 4>
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[CONV]]
 ;
   %shl = shl <2 x i32> <i32 1, i32 1>, %0
@@ -31,8 +31,8 @@ define <2 x i32> @icmp_eq_and_pow2_shl1_vec(<2 x i32> %0) {
 
 define i32 @icmp_ne_and_pow2_shl1(i32 %0) {
 ; CHECK-LABEL: @icmp_ne_and_pow2_shl1(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0:%.*]], 4
-; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP0:%.*]], 4
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %shl = shl i32 1, %0
@@ -44,8 +44,8 @@ define i32 @icmp_ne_and_pow2_shl1(i32 %0) {
 
 define <2 x i32> @icmp_ne_and_pow2_shl1_vec(<2 x i32> %0) {
 ; CHECK-LABEL: @icmp_ne_and_pow2_shl1_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i32> [[TMP0:%.*]], <i32 4, i32 4>
-; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP0:%.*]], <i32 4, i32 4>
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[CONV]]
 ;
   %shl = shl <2 x i32> <i32 1, i32 1>, %0
@@ -58,8 +58,8 @@ define <2 x i32> @icmp_ne_and_pow2_shl1_vec(<2 x i32> %0) {
 define i32 @icmp_eq_and_pow2_shl_pow2(i32 %0) {
 ; CHECK-LABEL: @icmp_eq_and_pow2_shl_pow2(
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP0:%.*]], 3
-; CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %shl = shl i32 2, %0
   %and = and i32 %shl, 16
@@ -71,8 +71,8 @@ define i32 @icmp_eq_and_pow2_shl_pow2(i32 %0) {
 define <2 x i32> @icmp_eq_and_pow2_shl_pow2_vec(<2 x i32> %0) {
 ; CHECK-LABEL: @icmp_eq_and_pow2_shl_pow2_vec(
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP0:%.*]], <i32 2, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
-; CHECK-NEXT:    ret <2 x i32> [[TMP3]]
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[CONV]]
 ;
   %shl = shl <2 x i32> <i32 4, i32 4>, %0
   %and = and <2 x i32> %shl, <i32 16, i32 16>
@@ -84,8 +84,8 @@ define <2 x i32> @icmp_eq_and_pow2_shl_pow2_vec(<2 x i32> %0) {
 define i32 @icmp_ne_and_pow2_shl_pow2(i32 %0) {
 ; CHECK-LABEL: @icmp_ne_and_pow2_shl_pow2(
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP0:%.*]], 3
-; CHECK-NEXT:    [[AND_LOBIT:%.*]] = zext i1 [[TMP2]] to i32
-; CHECK-NEXT:    ret i32 [[AND_LOBIT]]
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
+; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %shl = shl i32 2, %0
   %and = and i32 %shl, 16
@@ -97,8 +97,8 @@ define i32 @icmp_ne_and_pow2_shl_pow2(i32 %0) {
 define <2 x i32> @icmp_ne_and_pow2_shl_pow2_vec(<2 x i32> %0) {
 ; CHECK-LABEL: @icmp_ne_and_pow2_shl_pow2_vec(
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP0:%.*]], <i32 2, i32 2>
-; CHECK-NEXT:    [[AND_LOBIT:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
-; CHECK-NEXT:    ret <2 x i32> [[AND_LOBIT]]
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[CONV]]
 ;
   %shl = shl <2 x i32> <i32 4, i32 4>, %0
   %and = and <2 x i32> %shl, <i32 16, i32 16>
@@ -290,8 +290,8 @@ define i32 @icmp_eq_and_pow2_minus1_shl1_negative2(i32 %0) {
 
 define i32 @icmp_eq_and1_lshr_pow2(i32 %0) {
 ; CHECK-LABEL: @icmp_eq_and1_lshr_pow2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[TMP0:%.*]], 3
-; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP0:%.*]], 3
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %lshr = lshr i32 8, %0
@@ -303,8 +303,8 @@ define i32 @icmp_eq_and1_lshr_pow2(i32 %0) {
 
 define <2 x i32> @icmp_eq_and1_lshr_pow2_vec(<2 x i32> %0) {
 ; CHECK-LABEL: @icmp_eq_and1_lshr_pow2_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <2 x i32> [[TMP0:%.*]], <i32 3, i32 3>
-; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP0:%.*]], <i32 3, i32 3>
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[CONV]]
 ;
   %lshr = lshr <2 x i32> <i32 8, i32 8>, %0
@@ -316,8 +316,8 @@ define <2 x i32> @icmp_eq_and1_lshr_pow2_vec(<2 x i32> %0) {
 
 define i32 @icmp_ne_and1_lshr_pow2(i32 %0) {
 ; CHECK-LABEL: @icmp_ne_and1_lshr_pow2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[TMP0:%.*]], 3
-; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP0:%.*]], 3
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[TMP2]] to i32
 ; CHECK-NEXT:    ret i32 [[CONV]]
 ;
   %lshr = lshr i32 8, %0