[PATCH] D123231: [StructurizeCFG] Improve basic block ordering

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon marked 6 inline comments as done.
bcahoon added a comment.

In D123231#3584389 <https://reviews.llvm.org/D123231#3584389>, @ruiling wrote:

> I had tried a different approach to avoid inserting excessive number of boolean values during the loop-exit-unify in D127831 <https://reviews.llvm.org/D127831>. I just did some testing of that change against the LLVM IR Brendon shared with me. It shows the change could help reducing the number of registers as well as compile time. But it is sad that I still hit the error: "unhandled SGPR spill to memory" from SGPRSpillBuilder in SIRegisterInfo.cpp. Can the limitation be fixed? I did some register pressure comparison, seems the way I proposed would use much less VGPR than (D123230 <https://reviews.llvm.org/D123230> + D123231 <https://reviews.llvm.org/D123231>), but use more SGPR. I haven't looked further why there is such behavior difference. I think we need more investigation to know why. But looks like D127831 <https://reviews.llvm.org/D127831> might help us generate better code because we can use one VGPR as the backup storage for spilling of 64/32 SGPRs. And the idea used there is much easy to follow.

I tried your approach and it does improve compile-time, but I also see the register allocation error in another test. I'm not sure when that register allocation error will be fixed. But, it's surprising that it occurs because I do see register pressions improvements with your patch.


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