[PATCH] D127045: [BOLT] Use 32-bit MOV to zero 64-bit register in instrumentation code

[Amir Ayupov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG445bc88501f8: [BOLT] Use 32-bit MOV to zero 64-bit register in instrumentation code (authored by Amir).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127045/new/

https://reviews.llvm.org/D127045

Files:
  bolt/lib/Target/X86/X86MCPlusBuilder.cpp


Index: bolt/lib/Target/X86/X86MCPlusBuilder.cpp
===================================================================
--- bolt/lib/Target/X86/X86MCPlusBuilder.cpp
+++ bolt/lib/Target/X86/X86MCPlusBuilder.cpp
@@ -3129,7 +3129,12 @@
     case 1: Opcode = X86::MOV8ri; break;
     case 2: Opcode = X86::MOV16ri; break;
     case 4: Opcode = X86::MOV32ri; break;
-    case 8: Opcode = X86::MOV64ri; break;
+    // Writing to a 32-bit register always zeros the upper 32 bits of the
+    // full-width register
+    case 8:
+      Opcode = X86::MOV32ri;
+      Reg = getAliasSized(Reg, 4);
+      break;
     default:
       llvm_unreachable("Unexpected size");
     }


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