[llvm] 0fe13b5 - [X86] Add common CHECK prefix to nontemporal-3.ll tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 19 10:23:28 PDT 2022
Author: Simon Pilgrim
Date: 2022-06-19T18:23:19+01:00
New Revision: 0fe13b5f84abe1716f5991da057c801dc548a9ab
URL: https://github.com/llvm/llvm-project/commit/0fe13b5f84abe1716f5991da057c801dc548a9ab
DIFF: https://github.com/llvm/llvm-project/commit/0fe13b5f84abe1716f5991da057c801dc548a9ab.diff
LOG: [X86] Add common CHECK prefix to nontemporal-3.ll tests
Added:
Modified:
llvm/test/CodeGen/X86/nontemporal-3.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/nontemporal-3.ll b/llvm/test/CodeGen/X86/nontemporal-3.ll
index 90b50aedc9e1..5a16542f5139 100644
--- a/llvm/test/CodeGen/X86/nontemporal-3.ll
+++ b/llvm/test/CodeGen/X86/nontemporal-3.ll
@@ -1,162 +1,78 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefixes=SSE,SSE4A
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefixes=CHECK,SSE,SSE4A
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512
; Test codegen for under aligned nontemporal vector stores
; XMM versions.
define void @test_zero_v2f64_align1(<2 x double>* %dst) nounwind {
-; SSE-LABEL: test_zero_v2f64_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v2f64_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v2f64_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v2f64_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <2 x double> zeroinitializer, <2 x double>* %dst, align 1, !nontemporal !1
ret void
}
define void @test_zero_v4f32_align1(<4 x float>* %dst) nounwind {
-; SSE-LABEL: test_zero_v4f32_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v4f32_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v4f32_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v4f32_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <4 x float> zeroinitializer, <4 x float>* %dst, align 1, !nontemporal !1
ret void
}
define void @test_zero_v2i64_align1(<2 x i64>* %dst) nounwind {
-; SSE-LABEL: test_zero_v2i64_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v2i64_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v2i64_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v2i64_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <2 x i64> zeroinitializer, <2 x i64>* %dst, align 1, !nontemporal !1
ret void
}
define void @test_zero_v4i32_align1(<4 x i32>* %dst) nounwind {
-; SSE-LABEL: test_zero_v4i32_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v4i32_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v4i32_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v4i32_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <4 x i32> zeroinitializer, <4 x i32>* %dst, align 1, !nontemporal !1
ret void
}
define void @test_zero_v8i16_align1(<8 x i16>* %dst) nounwind {
-; SSE-LABEL: test_zero_v8i16_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v8i16_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v8i16_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v8i16_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <8 x i16> zeroinitializer, <8 x i16>* %dst, align 1, !nontemporal !1
ret void
}
define void @test_zero_v16i8_align1(<16 x i8>* %dst) nounwind {
-; SSE-LABEL: test_zero_v16i8_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v16i8_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v16i8_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v16i8_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: retq
store <16 x i8> zeroinitializer, <16 x i8>* %dst, align 1, !nontemporal !1
ret void
}
@@ -164,32 +80,14 @@ define void @test_zero_v16i8_align1(<16 x i8>* %dst) nounwind {
; YMM versions.
define void @test_zero_v4f64_align1(<4 x double>* %dst) nounwind {
-; SSE-LABEL: test_zero_v4f64_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: movntiq %rax, 24(%rdi)
-; SSE-NEXT: movntiq %rax, 16(%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v4f64_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: movntiq %rax, 24(%rdi)
-; AVX-NEXT: movntiq %rax, 16(%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v4f64_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: movntiq %rax, 24(%rdi)
-; AVX512-NEXT: movntiq %rax, 16(%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v4f64_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: movntiq %rax, 24(%rdi)
+; CHECK-NEXT: movntiq %rax, 16(%rdi)
+; CHECK-NEXT: retq
store <4 x double> zeroinitializer, <4 x double>* %dst, align 1, !nontemporal !1
ret void
}
@@ -593,44 +491,18 @@ define void @test_zero_v32i8_align16(<32 x i8>* %dst) nounwind {
; ZMM versions.
define void @test_zero_v8f64_align1(<8 x double>* %dst) nounwind {
-; SSE-LABEL: test_zero_v8f64_align1:
-; SSE: # %bb.0:
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: movntiq %rax, 24(%rdi)
-; SSE-NEXT: movntiq %rax, 16(%rdi)
-; SSE-NEXT: movntiq %rax, 8(%rdi)
-; SSE-NEXT: movntiq %rax, (%rdi)
-; SSE-NEXT: movntiq %rax, 56(%rdi)
-; SSE-NEXT: movntiq %rax, 48(%rdi)
-; SSE-NEXT: movntiq %rax, 40(%rdi)
-; SSE-NEXT: movntiq %rax, 32(%rdi)
-; SSE-NEXT: retq
-;
-; AVX-LABEL: test_zero_v8f64_align1:
-; AVX: # %bb.0:
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: movntiq %rax, 24(%rdi)
-; AVX-NEXT: movntiq %rax, 16(%rdi)
-; AVX-NEXT: movntiq %rax, 8(%rdi)
-; AVX-NEXT: movntiq %rax, (%rdi)
-; AVX-NEXT: movntiq %rax, 56(%rdi)
-; AVX-NEXT: movntiq %rax, 48(%rdi)
-; AVX-NEXT: movntiq %rax, 40(%rdi)
-; AVX-NEXT: movntiq %rax, 32(%rdi)
-; AVX-NEXT: retq
-;
-; AVX512-LABEL: test_zero_v8f64_align1:
-; AVX512: # %bb.0:
-; AVX512-NEXT: xorl %eax, %eax
-; AVX512-NEXT: movntiq %rax, 24(%rdi)
-; AVX512-NEXT: movntiq %rax, 16(%rdi)
-; AVX512-NEXT: movntiq %rax, 8(%rdi)
-; AVX512-NEXT: movntiq %rax, (%rdi)
-; AVX512-NEXT: movntiq %rax, 56(%rdi)
-; AVX512-NEXT: movntiq %rax, 48(%rdi)
-; AVX512-NEXT: movntiq %rax, 40(%rdi)
-; AVX512-NEXT: movntiq %rax, 32(%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: test_zero_v8f64_align1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movntiq %rax, 24(%rdi)
+; CHECK-NEXT: movntiq %rax, 16(%rdi)
+; CHECK-NEXT: movntiq %rax, 8(%rdi)
+; CHECK-NEXT: movntiq %rax, (%rdi)
+; CHECK-NEXT: movntiq %rax, 56(%rdi)
+; CHECK-NEXT: movntiq %rax, 48(%rdi)
+; CHECK-NEXT: movntiq %rax, 40(%rdi)
+; CHECK-NEXT: movntiq %rax, 32(%rdi)
+; CHECK-NEXT: retq
store <8 x double> zeroinitializer, <8 x double>* %dst, align 1, !nontemporal !1
ret void
}
More information about the llvm-commits
mailing list