[llvm] 91e2956 - [X86] Use X86 instead of X32 for i686 check prefixes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 18 07:16:27 PDT 2022
Author: Simon Pilgrim
Date: 2022-06-18T15:16:15+01:00
New Revision: 91e2956232e7893e8640f5a41d146aa87a1d577e
URL: https://github.com/llvm/llvm-project/commit/91e2956232e7893e8640f5a41d146aa87a1d577e
DIFF: https://github.com/llvm/llvm-project/commit/91e2956232e7893e8640f5a41d146aa87a1d577e.diff
LOG: [X86] Use X86 instead of X32 for i686 check prefixes
We try to reserve X32 check prefixes for gnux32 triple tests
Added:
Modified:
llvm/test/CodeGen/X86/known-bits-vector.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll
index 5170894e6330a..c46d4d3f29afa 100644
--- a/llvm/test/CodeGen/X86/known-bits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-bits-vector.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
define i32 @knownbits_mask_extract_sext(<8 x i16> %a0) nounwind {
-; X32-LABEL: knownbits_mask_extract_sext:
-; X32: # %bb.0:
-; X32-NEXT: vmovd %xmm0, %eax
-; X32-NEXT: andl $15, %eax
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_extract_sext:
+; X86: # %bb.0:
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: andl $15, %eax
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_extract_sext:
; X64: # %bb.0:
@@ -21,15 +21,15 @@ define i32 @knownbits_mask_extract_sext(<8 x i16> %a0) nounwind {
}
define float @knownbits_mask_extract_uitofp(<2 x i64> %a0) nounwind {
-; X32-LABEL: knownbits_mask_extract_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: pushl %eax
-; X32-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: vmovss %xmm0, (%esp)
-; X32-NEXT: flds (%esp)
-; X32-NEXT: popl %eax
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_extract_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: pushl %eax
+; X86-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: vmovss %xmm0, (%esp)
+; X86-NEXT: flds (%esp)
+; X86-NEXT: popl %eax
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_extract_uitofp:
; X64: # %bb.0:
@@ -43,15 +43,15 @@ define float @knownbits_mask_extract_uitofp(<2 x i64> %a0) nounwind {
}
define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nounwind {
-; X32-LABEL: knownbits_insert_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: vmovd %ecx, %xmm0
-; X32-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_insert_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: vmovd %ecx, %xmm0
+; X86-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_insert_uitofp:
; X64: # %bb.0:
@@ -72,12 +72,12 @@ define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nou
}
define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {
-; X32-LABEL: knownbits_mask_shuffle_sext:
-; X32: # %bb.0:
-; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_shuffle_sext:
+; X86: # %bb.0:
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_sext:
; X64: # %bb.0:
@@ -92,12 +92,12 @@ define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {
-; X32-LABEL: knownbits_mask_shuffle_shuffle_sext:
-; X32: # %bb.0:
-; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_shuffle_shuffle_sext:
+; X86: # %bb.0:
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; X86-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_shuffle_sext:
; X64: # %bb.0:
@@ -113,12 +113,12 @@ define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind {
-; X32-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
-; X32: # %bb.0:
-; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; X32-NEXT: vpmovsxwd %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
+; X86: # %bb.0:
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; X86-NEXT: vpmovsxwd %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
; X64: # %bb.0:
@@ -134,12 +134,12 @@ define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounw
}
define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_shuffle_uitofp:
; X64: # %bb.0:
@@ -154,10 +154,10 @@ define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind {
}
define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_or_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_or_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_or_shuffle_uitofp:
; X64: # %bb.0:
@@ -171,13 +171,13 @@ define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind {
}
define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_xor_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_xor_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_xor_shuffle_uitofp:
; X64: # %bb.0:
@@ -194,10 +194,10 @@ define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_shl_shuffle_lshr(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_shl_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_shl_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_shl_shuffle_lshr:
; X64: # %bb.0:
@@ -211,10 +211,10 @@ define <4 x i32> @knownbits_mask_shl_shuffle_lshr(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_ashr_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_ashr_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_ashr_shuffle_lshr:
; X64: # %bb.0:
@@ -228,10 +228,10 @@ define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_mask_mul_shuffle_shl:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_mul_shuffle_shl:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_mul_shuffle_shl:
; X64: # %bb.0:
@@ -245,10 +245,10 @@ define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) n
}
define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {
-; X32-LABEL: knownbits_mask_trunc_shuffle_shl:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_trunc_shuffle_shl:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_trunc_shuffle_shl:
; X64: # %bb.0:
@@ -262,10 +262,10 @@ define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_add_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_mask_add_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_add_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_add_shuffle_lshr:
; X64: # %bb.0:
@@ -280,10 +280,10 @@ define <4 x i32> @knownbits_mask_add_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1)
}
define <4 x i32> @knownbits_mask_sub_shuffle_lshr(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_sub_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_sub_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_sub_shuffle_lshr:
; X64: # %bb.0:
@@ -297,10 +297,10 @@ define <4 x i32> @knownbits_mask_sub_shuffle_lshr(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_udiv_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_mask_udiv_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_udiv_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_udiv_shuffle_lshr:
; X64: # %bb.0:
@@ -314,10 +314,10 @@ define <4 x i32> @knownbits_mask_udiv_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1)
}
define <4 x i32> @knownbits_urem_lshr(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_urem_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_urem_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_urem_lshr:
; X64: # %bb.0:
@@ -329,10 +329,10 @@ define <4 x i32> @knownbits_urem_lshr(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_urem_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_mask_urem_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_urem_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_urem_shuffle_lshr:
; X64: # %bb.0:
@@ -347,10 +347,10 @@ define <4 x i32> @knownbits_mask_urem_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1)
}
define <4 x i32> @knownbits_mask_srem_shuffle_lshr(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_srem_shuffle_lshr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_srem_shuffle_lshr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_srem_shuffle_lshr:
; X64: # %bb.0:
@@ -364,10 +364,10 @@ define <4 x i32> @knownbits_mask_srem_shuffle_lshr(<4 x i32> %a0) nounwind {
}
define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind {
-; X32-LABEL: knownbits_mask_bswap_shuffle_shl:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_bswap_shuffle_shl:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_bswap_shuffle_shl:
; X64: # %bb.0:
@@ -382,15 +382,15 @@ define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind {
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_mask_concat_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
-; X32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3]
-; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X32-NEXT: vcvtdq2ps %ymm0, %ymm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_concat_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; X86-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3]
+; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_concat_uitofp:
; X64: # %bb.0:
@@ -409,12 +409,12 @@ define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) n
}
define <4 x float> @knownbits_lshr_bitcast_shuffle_uitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
-; X32-LABEL: knownbits_lshr_bitcast_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpsrlq $1, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_lshr_bitcast_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpsrlq $1, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_lshr_bitcast_shuffle_uitofp:
; X64: # %bb.0:
@@ -430,13 +430,13 @@ define <4 x float> @knownbits_lshr_bitcast_shuffle_uitofp(<2 x i64> %a0, <4 x i3
}
define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) {
-; X32-LABEL: knownbits_smax_smin_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_smax_smin_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_smax_smin_shuffle_uitofp:
; X64: # %bb.0:
@@ -455,12 +455,12 @@ declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) {
-; X32-LABEL: knownbits_umin_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_umin_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_umin_shuffle_uitofp:
; X64: # %bb.0:
@@ -476,10 +476,10 @@ define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) {
declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @knownbits_umax_shuffle_ashr(<4 x i32> %a0) {
-; X32-LABEL: knownbits_umax_shuffle_ashr:
-; X32: # %bb.0:
-; X32-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_umax_shuffle_ashr:
+; X86: # %bb.0:
+; X86-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_umax_shuffle_ashr:
; X64: # %bb.0:
@@ -493,13 +493,13 @@ define <4 x i32> @knownbits_umax_shuffle_ashr(<4 x i32> %a0) {
declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) {
-; X32-LABEL: knownbits_mask_umax_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_umax_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpmaxud {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_umax_shuffle_uitofp:
; X64: # %bb.0:
@@ -516,10 +516,10 @@ define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) {
}
define <4 x i32> @knownbits_mask_bitreverse_ashr(<4 x i32> %a0) {
-; X32-LABEL: knownbits_mask_bitreverse_ashr:
-; X32: # %bb.0:
-; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_mask_bitreverse_ashr:
+; X86: # %bb.0:
+; X86-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_bitreverse_ashr:
; X64: # %bb.0:
@@ -534,15 +534,15 @@ declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) nounwind readnone
; If we don't know that the input isn't INT_MIN we can't combine to sitofp
define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
-; X32-LABEL: knownbits_abs_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpabsd %xmm0, %xmm0
-; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-NEXT: vpsrld $16, %xmm0, %xmm0
-; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_abs_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpabsd %xmm0, %xmm0
+; X86-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X86-NEXT: vpsrld $16, %xmm0, %xmm0
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X86-NEXT: vsubps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vaddps %xmm0, %xmm1, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_abs_uitofp:
; X64: # %bb.0:
@@ -561,13 +561,13 @@ define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
}
define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
-; X32-LABEL: knownbits_or_abs_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
-; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
-; X32-NEXT: vpabsd %xmm0, %xmm0
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_or_abs_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
+; X86-NEXT: vpabsd %xmm0, %xmm0
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_or_abs_uitofp:
; X64: # %bb.0:
@@ -586,22 +586,22 @@ define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
}
define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind {
-; X32-LABEL: knownbits_and_select_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $16, %esp
-; X32-NEXT: vmovaps 8(%ebp), %xmm3
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
-; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: movl %ebp, %esp
-; X32-NEXT: popl %ebp
-; X32-NEXT: retl
+; X86-LABEL: knownbits_and_select_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: andl $-16, %esp
+; X86-NEXT: subl $16, %esp
+; X86-NEXT: vmovaps 8(%ebp), %xmm3
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
+; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: movl %ebp, %esp
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_and_select_shuffle_uitofp:
; X64: # %bb.0:
@@ -622,22 +622,22 @@ define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32>
}
define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind {
-; X32-LABEL: knownbits_lshr_and_select_shuffle_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $16, %esp
-; X32-NEXT: vmovaps 8(%ebp), %xmm3
-; X32-NEXT: vpsrld $5, %xmm2, %xmm2
-; X32-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
-; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
-; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
-; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
-; X32-NEXT: movl %ebp, %esp
-; X32-NEXT: popl %ebp
-; X32-NEXT: retl
+; X86-LABEL: knownbits_lshr_and_select_shuffle_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: movl %esp, %ebp
+; X86-NEXT: andl $-16, %esp
+; X86-NEXT: subl $16, %esp
+; X86-NEXT: vmovaps 8(%ebp), %xmm3
+; X86-NEXT: vpsrld $5, %xmm2, %xmm2
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
+; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
+; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
+; X86-NEXT: movl %ebp, %esp
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_lshr_and_select_shuffle_uitofp:
; X64: # %bb.0:
@@ -658,13 +658,13 @@ define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x
}
define <2 x double> @knownbits_lshr_subvector_uitofp(<4 x i32> %x) {
-; X32-LABEL: knownbits_lshr_subvector_uitofp:
-; X32: # %bb.0:
-; X32-NEXT: vpsrld $2, %xmm0, %xmm1
-; X32-NEXT: vpsrld $1, %xmm0, %xmm0
-; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
-; X32-NEXT: vcvtdq2pd %xmm0, %xmm0
-; X32-NEXT: retl
+; X86-LABEL: knownbits_lshr_subvector_uitofp:
+; X86: # %bb.0:
+; X86-NEXT: vpsrld $2, %xmm0, %xmm1
+; X86-NEXT: vpsrld $1, %xmm0, %xmm0
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
+; X86-NEXT: vcvtdq2pd %xmm0, %xmm0
+; X86-NEXT: retl
;
; X64-LABEL: knownbits_lshr_subvector_uitofp:
; X64: # %bb.0:
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