[PATCH] D127731: WIP: [MachineVerifier] Try harder to verify analyses

[Daniil Fukalov via Phabricator via llvm-commits]

dfukalov added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll:2285
 ; SI-NEXT:    buffer_load_ubyte v3, off, s[0:3], 0
-; SI-NEXT:    s_load_dword s0, s[0:1], 0x0
+; SI-NEXT:    s_load_dword s4, s[0:1], 0x0
 ; SI-NEXT:    s_waitcnt vmcnt(3)
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I'm wondering the test started to use one more SReg for SI and VI after the patch.


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Comment at: llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll:2407
   store i32 %retval.sroa.0.0.insert.insert, i32 addrspace(1)* undef, align 1
   br label %for.body.i
 }
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But it doesn't fix SRegs usage...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127731/new/

https://reviews.llvm.org/D127731