[PATCH] D128106: [PowerPC] Add support for G_ADD and G_SUB.

[Kai Nacke via Phabricator via llvm-commits]

Kai created this revision.
Kai added reviewers: nemanjai, saghir, tschuett, arsenm, aemerson.
Herald added subscribers: shchenz, kbarton, hiraditya.
Herald added a project: All.
Kai requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Extends the global isel implementation to support G_ADD and G_SUB.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128106

Files:
  llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
  llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
  llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll


Index: llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple ppc64le-linux -global-isel -o - < %s | FileCheck %s -check-prefixes=CHECK,LINUX
+
+; CHECK-LABEL: test_add:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i64 @test_add(i64 %a, i64 %b) {
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+; CHECK-LABEL: test_sub:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i64 @test_sub(i64 %a, i64 %b) {
+  %res = sub i64 %a, %b
+  ret i64 %res
+}
Index: llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll
+++ llvm/test/CodeGen/PowerPC/GlobalISel/ppc-irtranslator.ll
@@ -32,3 +32,25 @@
   %res = xor i64 %a, %b
   ret i64 %res
 }
+
+; CHECK-LABEL: name: addi64
+; CHECK:       [[ARG1:%[0-9]+]]:_(s64) = COPY $x3
+; CHECK-NEXT:  [[ARG2:%[0-9]+]]:_(s64) = COPY $x4
+; CHECK-NEXT:  [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
+; CHECK-NEXT:  $x3 = COPY [[RES]]
+; CHECK-NEXT:  BLR8 implicit $lr8, implicit $rm, implicit $x3
+define i64 @addi64(i64 %a, i64 %b) {
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+; CHECK-LABEL: name: subi64
+; CHECK:       [[ARG1:%[0-9]+]]:_(s64) = COPY $x3
+; CHECK-NEXT:  [[ARG2:%[0-9]+]]:_(s64) = COPY $x4
+; CHECK-NEXT:  [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK-NEXT:  $x3 = COPY [[RES]]
+; CHECK-NEXT:  BLR8 implicit $lr8, implicit $rm, implicit $x3
+define i64 @subi64(i64 %a, i64 %b) {
+  %res = sub i64 %a, %b
+  ret i64 %res
+}
Index: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -66,6 +66,9 @@
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
+    // Arithmetic ops.
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
Index: llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -27,5 +27,8 @@
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ADD, G_SUB})
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }


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