[PATCH] D128023: [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1841
                 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
-  def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
+  def : Pat<(vti.Vector (riscv_vrgather_vv_vl (vti.Vector srcvalue),
+                                              vti.RegClass:$rs2,
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Fraser knows this but I'll mention it for @reames. `srcvalue` happens to be hole in the isel pattern system that causes the operand to be completely ignored. Since the mask is true_mask here we don't need the value. This allows the operand to be dropped even if it isn't undef. I think we get an error if we capture an operand and then don't use it in the output pattern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128023/new/

https://reviews.llvm.org/D128023