[llvm] 4d245f1 - [RISCV] Move store policy and mask reg ops into demanded handling in InsertVSETVLI
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 17 12:12:53 PDT 2022
Author: Philip Reames
Date: 2022-06-17T12:09:50-07:00
New Revision: 4d245f1bc2e2615c0e6f7fb79cac9a4d97dc9847
URL: https://github.com/llvm/llvm-project/commit/4d245f1bc2e2615c0e6f7fb79cac9a4d97dc9847
DIFF: https://github.com/llvm/llvm-project/commit/4d245f1bc2e2615c0e6f7fb79cac9a4d97dc9847.diff
LOG: [RISCV] Move store policy and mask reg ops into demanded handling in InsertVSETVLI
Doing so let's the post-mutation pass leverage the demanded info to rewrite vsetvlis before a store/mask-op to eliminate later vsetvlis.
Sorry for the lack of store test change; all of my attempts to write something reasonable have been handled through existing logic.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 7fa0056b3a6fc..3210346583356 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -303,6 +303,8 @@ static Optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
}
}
+/// Return true if this is an operation on mask registers. Note that
+/// this includes both arithmetic/logical ops and load/store (vlm/vsm).
static bool isMaskRegOp(const MachineInstr &MI) {
if (RISCVII::hasSEWOp(MI.getDesc().TSFlags)) {
const unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm();
@@ -411,6 +413,12 @@ static DemandedFields getDemanded(const MachineInstr &MI) {
Res.LMUL = false;
}
+ // Store instructions don't use the policy fields.
+ if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) {
+ Res.TailPolicy = false;
+ Res.MaskPolicy = false;
+ }
+
// A splat of 0/-1 is always a splat of 0/-1, regardless of etype.
// TODO: We're currently demanding VL + SEWLMULRatio which is sufficient
// but not neccessary. What we really need is VLInBytes.
@@ -419,6 +427,15 @@ static DemandedFields getDemanded(const MachineInstr &MI) {
Res.LMUL = false;
}
+ // If this is a mask reg operation, it only cares about VLMAX.
+ // TODO: Possible extensions to this logic
+ // * Probably ok if available VLMax is larger than demanded
+ // * The policy bits can probably be ignored..
+ if (isMaskRegOp(MI)) {
+ Res.SEW = false;
+ Res.LMUL = false;
+ }
+
return Res;
}
@@ -590,24 +607,7 @@ class VSETVLIInfo {
if (hasSameVTYPE(Require))
return true;
- // If this is a mask reg operation, it only cares about VLMAX.
- // FIXME: Mask reg operations are probably ok if "this" VLMAX is larger
- // than "Require".
- // FIXME: The policy bits can probably be ignored for mask reg operations.
- if (isMaskRegOp(MI) && hasSameVLMAX(Require) &&
- TailAgnostic == Require.TailAgnostic &&
- MaskAgnostic == Require.MaskAgnostic)
- return true;
-
- DemandedFields Used = getDemanded(MI);
- // Store instructions don't use the policy fields.
- // TODO: Move this into getDemanded; it is here only to avoid changing
- // behavior of the post pass in an otherwise NFC code restructure.
- uint64_t TSFlags = MI.getDesc().TSFlags;
- if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) {
- Used.TailPolicy = false;
- Used.MaskPolicy = false;
- }
+ const DemandedFields Used = getDemanded(MI);
return areCompatibleVTYPEs(encodeVTYPE(), Require.encodeVTYPE(), Used);
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
index 4c0d95bbf665a..c264646adc5eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
@@ -7,10 +7,9 @@
define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) {
; CHECK-LABEL: sextload_v2i1_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: ret
%y = load <2 x i1>, <2 x i1>* %x
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