[PATCH] D128045: [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c

Thorsten via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 17 11:36:03 PDT 2022

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tschuett added a comment.

Sorry! Your tablegen predicate is `HasSVE2orSME`. Your .ll target features are sve and sve2?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128045/new/

https://reviews.llvm.org/D128045

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