[PATCH] D128065: [AArch64][SVE] Fold target specific ext/trunc nodes into loads/stores

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
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Due to the way fixed length SVE lowering works, we sometimes introduce
ext/trunc nodes very late, these nodes then immediately get converted
into target specific nodes (UUNPKLO/UZP1) before they get a chance to be
folded into a load/store.

This patch introduces target specific dag combines for these nodes so that
we can still create extending loads/truncating stores out of them.

Additionally this patch introduces a PTRUE dag combine such that we can
correct the register size of a PTRUE very late, as is done in these new
dag combines.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128065

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

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