[PATCH] D127710: [SelectionDAG] Enable WidenVecOp_VECREDUCE_SEQ for scalable vector

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!



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Comment at: llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll:1081
+
+define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
+; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:
----------------
Jimerlife wrote:
> sdesmalen wrote:
> > sdesmalen wrote:
> > > Could you also add `@vreduce_ord_fadd_nxv6f16` and `@vreduce_ord_fadd_nxv10f16`  to llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll as well ? (and then just re-generate the CHECK lines using the `update_lcc_test_checks.py` script)
> > And `@vreduce_ord_fadd_nxv12f16` as well.
> This vecreduce-fadd-legalization-strict.ll file is only for NEON feature. So, I add tests in sve-fp-reduce.ll. Is it OK?
Thanks, I hadn't seen that. That's fine!


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https://reviews.llvm.org/D127710