[PATCH] D128038: [LegalizeTypes][NFC] Add an assert to WidenVecRes_EXTRACT_SUBVECTOR and adjust some code
WangLian via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 17 02:29:03 PDT 2022
Jimerlife created this revision.
Jimerlife added reviewers: sdesmalen, david-arm, craig.topper, frasercrmck, benshi001.
Jimerlife added a project: LLVM.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
Jimerlife requested review of this revision.
Herald added subscribers: llvm-commits, jacquesguan.
I think idx should be multiple of subvector minimum vector length.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128038
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4728,11 +4728,11 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- EVT VT = N->getValueType(0);
- EVT EltVT = VT.getVectorElementType();
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- SDValue InOp = N->getOperand(0);
- SDValue Idx = N->getOperand(1);
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+ SDValue InOp = N->getOperand(0);
+ SDValue Idx = N->getOperand(1);
SDLoc dl(N);
auto InOpTypeAction = getTypeAction(InOp.getValueType());
@@ -4749,6 +4749,9 @@
// Check if we can extract from the vector.
unsigned WidenNumElts = WidenVT.getVectorMinNumElements();
unsigned InNumElts = InVT.getVectorMinNumElements();
+ unsigned VTNumElts = VT.getVectorMinNumElements();
+ assert(IdxVal % VTNumElts == 0 &&
+ "Expected Idx to be a multiple of subvector minimum vector length");
if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
@@ -4762,8 +4765,7 @@
// nxv2i64 extract_subvector(nxv16i64, 8)
// nxv2i64 extract_subvector(nxv16i64, 10)
// undef)
- unsigned VTNElts = VT.getVectorMinNumElements();
- unsigned GCD = greatestCommonDivisor(VTNElts, WidenNumElts);
+ unsigned GCD = greatestCommonDivisor(VTNumElts, WidenNumElts);
assert((IdxVal % GCD) == 0 && "Expected Idx to be a multiple of the broken "
"down type's element count");
EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
@@ -4772,7 +4774,7 @@
if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) {
SmallVector<SDValue> Parts;
unsigned I = 0;
- for (; I < VTNElts / GCD; ++I)
+ for (; I < VTNumElts / GCD; ++I)
Parts.push_back(
DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, InOp,
DAG.getVectorIdxConstant(IdxVal + I * GCD, dl)));
@@ -4789,9 +4791,8 @@
// We could try widening the input to the right length but for now, extract
// the original elements, fill the rest with undefs and build a vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- unsigned NumElts = VT.getVectorNumElements();
unsigned i;
- for (i = 0; i < NumElts; ++i)
+ for (i = 0; i < VTNumElts; ++i)
Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getVectorIdxConstant(IdxVal + i, dl));
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