[llvm] 880ac51 - [RISCV][NFC] Add load/store instructions in rv64*-invalid.s

[via llvm-commits]

Author: ping.deng
Date: 2022-06-17T06:53:19Z
New Revision: 880ac5189d638e2b46d63027bc39419262e139c2

URL: https://github.com/llvm/llvm-project/commit/880ac5189d638e2b46d63027bc39419262e139c2
DIFF: https://github.com/llvm/llvm-project/commit/880ac5189d638e2b46d63027bc39419262e139c2.diff

LOG: [RISCV][NFC] Add load/store instructions in rv64*-invalid.s

Reviewed By: benshi001, sunshaoce

Differential Revision: https://reviews.llvm.org/D127721

Added: 
    

Modified: 
    llvm/test/MC/RISCV/rv64zdinx-invalid.s
    llvm/test/MC/RISCV/rv64zfh-invalid.s
    llvm/test/MC/RISCV/rv64zfinx-invalid.s
    llvm/test/MC/RISCV/rv64zhinx-invalid.s
    llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Removed: 
    


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diff  --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
index 8ba06963a553e..4f82da0d792ab 100644
--- a/llvm/test/MC/RISCV/rv64zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
@@ -1,6 +1,12 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s
 
-# Invalid Instructions
+# Not support float registers
+fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
+ld a0, -2049(a1) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Invalid instructions
+fsd a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+sd fa4, 64(sp) # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
 fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9:  error: invalid operand for instruction
 

diff  --git a/llvm/test/MC/RISCV/rv64zfh-invalid.s b/llvm/test/MC/RISCV/rv64zfh-invalid.s
index f7c1ea0e79437..5cde33d15425f 100644
--- a/llvm/test/MC/RISCV/rv64zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfh-invalid.s
@@ -1,6 +1,17 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zfh < %s 2>&1 | \
 # RUN:   FileCheck %s
 
+# Out of range immediates
+## simm12
+flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Memory operand not formatted correctly
+flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+
 # Integer registers where FP regs are expected
 fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

diff  --git a/llvm/test/MC/RISCV/rv64zfinx-invalid.s b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
index 5815a85cdf0ea..197a6c28f97f3 100644
--- a/llvm/test/MC/RISCV/rv64zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s
 
+# Not support float registers
+flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
+
 # Invalid instructions
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 

diff  --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
index 90fb08b5af7c2..33693f114f8fd 100644
--- a/llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,6 +1,10 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
+# Not support float registers
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)
+
 # Invalid instructions
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 

diff  --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
index 9a7e8b0c675d7..cf5a33894c81c 100644
--- a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,6 +1,10 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
+
+# Not support float registers
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)
 
 # Invalid instructions
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction