[PATCH] D127203: [LoongArch] Add codegen support for the bitwise binary operations and part of other operations

[WÁNG Xuěruì via Phabricator via llvm-commits]

xen0n added inline comments.


================
Comment at: llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll:26
+; LA32-NEXT:    movcf2gr $a0, $fcc0
+; LA32-NEXT:    andi $a0, $a0, 1
+; LA32-NEXT:    jirl $zero, $ra, 0
----------------
SixWeining wrote:
> Sorry, this instruction is not necessary as the [[ https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_movgr2cf_movcf2gr | ISA ]] says:
> 
> > MOVCF2GR writes the value of the condition flag register cj into the lowest bit of the general register rd and clears the other bits.
> 
> Let me remove it.
> 
Ah, I checked the original text, and unfortunately there seems to be a translation error:

{F23486317}

> MOVCF2GR 将条件标志寄存器 cj 的值写入通用寄存器 rd 的最低一比特。
>
> `GR[rd][0] = CFR[cj]`

which means this instead, for anyone knowing Chinese:

> MOVCF2GR writes the value of conditional flag register cj to the lowest bit of GPR rd.

this also agrees with the pseudo-code.

So, if we don't want UB in case the destination of `movcf2gr` cannot be statically proven to have a sane value, the `andi` is still needed... And the translation error should be fixed.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127203/new/

https://reviews.llvm.org/D127203