[PATCH] D127203: [LoongArch] Add codegen support for the bitwise binary operations and part of other operations

[Lu Weining via Phabricator via llvm-commits]

SixWeining added inline comments.


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Comment at: llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll:26
+; LA32-NEXT:    movcf2gr $a0, $fcc0
+; LA32-NEXT:    andi $a0, $a0, 1
+; LA32-NEXT:    jirl $zero, $ra, 0
----------------
Sorry, this instruction is not necessary as the [[ https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_movgr2cf_movcf2gr | ISA ]] says:

> MOVCF2GR writes the value of the condition flag register cj into the lowest bit of the general register rd and clears the other bits.

Let me remove it.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127203/new/

https://reviews.llvm.org/D127203