[PATCH] D127939: [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

[WangLian via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG16215eb9790a: [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add… (authored by Jimerlife).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127939/new/

https://reviews.llvm.org/D127939

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll


Index: llvm/test/CodeGen/RISCV/rvv/stepvector.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/stepvector.ll
+++ llvm/test/CodeGen/RISCV/rvv/stepvector.ll
@@ -167,6 +167,18 @@
   ret <vscale x 2 x i16> %v
 }
 
+declare <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+
+define <vscale x 2 x i15> @stepvector_nxv2i15() {
+; CHECK-LABEL: stepvector_nxv2i15:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    ret
+  %v = call <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15()
+  ret <vscale x 2 x i15> %v
+}
+
 declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16()
 
 define <vscale x 3 x i16> @stepvector_nxv3i16() {
@@ -515,7 +527,6 @@
   ret <vscale x 8 x i64> %3
 }
 
-
 define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {
 ; CHECK-LABEL: shl_stepvector_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -5277,7 +5277,8 @@
   SDLoc dl(N);
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
-  assert(NOutVT.isVector() && "Type must be promoted to a vector type");
+  assert(NOutVT.isScalableVector() &&
+         "Type must be promoted to a scalable vector type");
   APInt StepVal = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
   return DAG.getStepVector(dl, NOutVT,
                            StepVal.sext(NOutVT.getScalarSizeInBits()));


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