[PATCH] D128006: [RISCV] Avoid changing etype for splat of 0 or -1

[Philip Reames via Phabricator via llvm-commits]

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A splat of the values 0 and -1 as sign extended 12 bit immediates are always the same bit pattern regardless of the etype used to perform the operation.  As a result, we can sometimes avoid introducing a vsetvli just for the purposes of a splat.

Looking at the diffs, we don't get a huge amount of immediate value out of this.  We mostly push the vsetvli one instruction down, usually in front of a vmerge.  We also don't get the corresponding fixed length vector cases because VL typically is changed despite the actual bits written being the same.  Both of these are areas I plan to explore in future patches.

Interestingly, we need both the forward and backward implementation here to avoid practical regressions.  If we implement only the forward direction, we loose the ability to mutate a prior vsetvli and eliminate a later one entirely.  The duplication in this patch will disappear once we finish merging the demanded analysis code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128006

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

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