[llvm] 89a11eb - [RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 16 11:14:34 PDT 2022
Author: Philip Reames
Date: 2022-06-16T11:14:21-07:00
New Revision: 89a11ebd8e10b7cf108110687b1847cd7fbfbd02
URL: https://github.com/llvm/llvm-project/commit/89a11ebd8e10b7cf108110687b1847cd7fbfbd02
DIFF: https://github.com/llvm/llvm-project/commit/89a11ebd8e10b7cf108110687b1847cd7fbfbd02.diff
LOG: [RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector
If we're writing to an undef vector (i.e. implicit_def), we can change the value of bits outside the requested write without consequence. This allows us to avoid a VSETVLI just for narrowing the value written.
Differential Revision: https://reviews.llvm.org/D127880
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 2c0e7fd61d9fc..cf47c5f64f5b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -562,15 +562,6 @@ class VSETVLIInfo {
if (SEW == Require.SEW)
return true;
- // For vmv.s.x and vfmv.s.f, there is only two behaviors, VL = 0 and VL > 0.
- // So it's compatible when we could make sure that both VL be the same
- // situation.
- if (isScalarMoveInstr(MI) && Require.hasAVLImm() &&
- ((hasNonZeroAVL() && Require.hasNonZeroAVL()) ||
- (hasZeroAVL() && Require.hasZeroAVL())) &&
- hasSameSEW(Require) && hasSamePolicy(Require))
- return true;
-
// The AVL must match.
if (!hasSameAVL(Require))
return false;
@@ -992,6 +983,22 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
if (CurInfo.isCompatible(MI, Require))
return false;
+ // For vmv.s.x and vfmv.s.f, there is only two behaviors, VL = 0 and VL > 0.
+ // So it's compatible when we could make sure that both VL be the same
+ // situation. Additionally, if writing to an implicit_def operand, we
+ // don't need to preserve any other bits and are thus compatible with any
+ // larger etype, and can disregard policy bits.
+ if (isScalarMoveInstr(MI) &&
+ ((CurInfo.hasNonZeroAVL() && Require.hasNonZeroAVL()) ||
+ (CurInfo.hasZeroAVL() && Require.hasZeroAVL()))) {
+ auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
+ if (VRegDef && VRegDef->isImplicitDef() &&
+ CurInfo.getSEW() >= Require.getSEW())
+ return false;
+ if (CurInfo.hasSameSEW(Require) && CurInfo.hasSamePolicy(Require))
+ return false;
+ }
+
// We didn't find a compatible value. If our AVL is a virtual register,
// it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
// and the last VL/VTYPE we observed is the same, we don't need a
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
index e5b3f1872088b..a7c15c99809bd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
@@ -179,7 +179,6 @@ define void @bitreverse_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4
; RV32-NEXT: li a5, 5
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.v.i v11, 0
@@ -726,7 +725,6 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV32-NEXT: li a5, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
@@ -871,7 +869,6 @@ define void @bitreverse_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a5
; LMULMAX1-RV32-NEXT: li a6, 5
-; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
index 7a156ea7a8f8e..f133e6e074868 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
@@ -85,7 +85,6 @@ define void @bswap_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4
; RV32-NEXT: li a5, 5
-; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.v.i v11, 0
@@ -353,7 +352,6 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV32-NEXT: li a5, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
@@ -447,7 +445,6 @@ define void @bswap_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV32-NEXT: li a6, 5
-; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 2ca0850cdde36..c45ac2a59ab65 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -42,16 +42,13 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x,
; LMULMAX1-NEXT: vrgather.vi v12, v8, 0
; LMULMAX1-NEXT: vrgather.vi v12, v9, 3, v0.t
; LMULMAX1-NEXT: li a0, 8
-; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.s.x v0, a0
-; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vrgather.vi v8, v10, 0
-; LMULMAX1-NEXT: vrgather.vi v8, v11, 3, v0.t
+; LMULMAX1-NEXT: vrgather.vi v9, v10, 0
; LMULMAX1-NEXT: li a0, 3
-; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; LMULMAX1-NEXT: vmv.s.x v0, a0
-; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; LMULMAX1-NEXT: vmerge.vvm v8, v8, v12, v0
+; LMULMAX1-NEXT: vmv.s.x v8, a0
+; LMULMAX1-NEXT: vrgather.vi v9, v11, 3, v0.t
+; LMULMAX1-NEXT: vmv.v.v v0, v8
+; LMULMAX1-NEXT: vmerge.vvm v8, v9, v12, v0
; LMULMAX1-NEXT: ret
;
; LMULMAX2-LABEL: hang_when_merging_stores_after_legalization:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
index f5fcc2991b80c..20350200f9944 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
@@ -44,11 +44,9 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
; RV32-V128-NEXT: vid.v v10
; RV32-V128-NEXT: vsrl.vi v14, v10, 1
; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
; RV32-V128-NEXT: li a0, 10
-; RV32-V128-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-V128-NEXT: vmv.s.x v0, a0
-; RV32-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v14, v0.t
; RV32-V128-NEXT: vmv.v.v v8, v10
; RV32-V128-NEXT: ret
@@ -60,11 +58,9 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-V128-NEXT: vid.v v10
; RV64-V128-NEXT: vsrl.vi v14, v10, 1
-; RV64-V128-NEXT: vrgather.vv v10, v8, v14
; RV64-V128-NEXT: li a0, 10
-; RV64-V128-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-V128-NEXT: vmv.s.x v0, a0
-; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV64-V128-NEXT: vrgather.vv v10, v8, v14
; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t
; RV64-V128-NEXT: vmv.v.v v8, v10
; RV64-V128-NEXT: ret
@@ -75,11 +71,9 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
; RV32-V512-NEXT: vid.v v10
; RV32-V512-NEXT: vsrl.vi v11, v10, 1
; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11
; RV32-V512-NEXT: li a0, 10
-; RV32-V512-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-V512-NEXT: vmv.s.x v0, a0
-; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11
; RV32-V512-NEXT: vrgatherei16.vv v10, v9, v11, v0.t
; RV32-V512-NEXT: vmv.v.v v8, v10
; RV32-V512-NEXT: ret
@@ -89,11 +83,9 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
; RV64-V512-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; RV64-V512-NEXT: vid.v v10
; RV64-V512-NEXT: vsrl.vi v11, v10, 1
-; RV64-V512-NEXT: vrgather.vv v10, v8, v11
; RV64-V512-NEXT: li a0, 10
-; RV64-V512-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-V512-NEXT: vmv.s.x v0, a0
-; RV64-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-V512-NEXT: vrgather.vv v10, v8, v11
; RV64-V512-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-V512-NEXT: vmv.v.v v8, v10
; RV64-V512-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
index 951ff054a11e5..16881294f61af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
@@ -135,11 +135,9 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
; RV32-NEXT: addi a0, a0, %lo(.LCPI6_0)
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle16.v v14, (a0)
-; RV32-NEXT: vrgatherei16.vv v12, v8, v14
; RV32-NEXT: li a0, 8
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV32-NEXT: vrgatherei16.vv v12, v8, v14
; RV32-NEXT: vrgather.vi v12, v10, 1, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
@@ -150,11 +148,9 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
; RV64-NEXT: addi a0, a0, %lo(.LCPI6_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v14, (a0)
-; RV64-NEXT: vrgather.vv v12, v8, v14
; RV64-NEXT: li a0, 8
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
-; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV64-NEXT: vrgather.vv v12, v8, v14
; RV64-NEXT: vrgather.vi v12, v10, 1, v0.t
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
@@ -201,15 +197,14 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; RV32-NEXT: vid.v v10
+; RV32-NEXT: vid.v v12
; RV32-NEXT: li a0, 3
-; RV32-NEXT: vmul.vx v12, v10, a0
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
+; RV32-NEXT: lui a1, %hi(.LCPI8_0)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI8_0)
+; RV32-NEXT: vlse64.v v10, (a1), zero
+; RV32-NEXT: vmul.vx v12, v12, a0
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: lui a0, %hi(.LCPI8_0)
-; RV32-NEXT: addi a0, a0, %lo(.LCPI8_0)
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
@@ -217,15 +212,13 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV64-LABEL: vrgather_shuffle_vx_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV64-NEXT: vid.v v10
-; RV64-NEXT: li a0, 3
-; RV64-NEXT: vmul.vx v12, v10, a0
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV64-NEXT: vmv.s.x v0, a0
+; RV64-NEXT: vid.v v12
; RV64-NEXT: lui a0, %hi(.LCPI8_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI8_0)
-; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vlse64.v v10, (a0), zero
+; RV64-NEXT: li a0, 3
+; RV64-NEXT: vmv.s.x v0, a0
+; RV64-NEXT: vmul.vx v12, v12, a0
; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
index 217e2e4731096..d39b6a81a70bf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
@@ -57,11 +57,9 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; RV32-V128-NEXT: vid.v v10
; RV32-V128-NEXT: vsrl.vi v14, v10, 1
; RV32-V128-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
; RV32-V128-NEXT: li a0, 10
-; RV32-V128-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-V128-NEXT: vmv.s.x v0, a0
-; RV32-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV32-V128-NEXT: vrgatherei16.vv v10, v8, v14
; RV32-V128-NEXT: vrgatherei16.vv v10, v12, v14, v0.t
; RV32-V128-NEXT: vmv.v.v v8, v10
; RV32-V128-NEXT: ret
@@ -73,11 +71,9 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-V128-NEXT: vid.v v10
; RV64-V128-NEXT: vsrl.vi v14, v10, 1
-; RV64-V128-NEXT: vrgather.vv v10, v8, v14
; RV64-V128-NEXT: li a0, 10
-; RV64-V128-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-V128-NEXT: vmv.s.x v0, a0
-; RV64-V128-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV64-V128-NEXT: vrgather.vv v10, v8, v14
; RV64-V128-NEXT: vrgather.vv v10, v12, v14, v0.t
; RV64-V128-NEXT: vmv.v.v v8, v10
; RV64-V128-NEXT: ret
@@ -88,11 +84,9 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; RV32-V512-NEXT: vid.v v10
; RV32-V512-NEXT: vsrl.vi v11, v10, 1
; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
-; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11
; RV32-V512-NEXT: li a0, 10
-; RV32-V512-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-V512-NEXT: vmv.s.x v0, a0
-; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11
; RV32-V512-NEXT: vrgatherei16.vv v10, v9, v11, v0.t
; RV32-V512-NEXT: vmv.v.v v8, v10
; RV32-V512-NEXT: ret
@@ -102,11 +96,9 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; RV64-V512-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; RV64-V512-NEXT: vid.v v10
; RV64-V512-NEXT: vsrl.vi v11, v10, 1
-; RV64-V512-NEXT: vrgather.vv v10, v8, v11
; RV64-V512-NEXT: li a0, 10
-; RV64-V512-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-V512-NEXT: vmv.s.x v0, a0
-; RV64-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu
+; RV64-V512-NEXT: vrgather.vv v10, v8, v11
; RV64-V512-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-V512-NEXT: vmv.v.v v8, v10
; RV64-V512-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index a67319cd5b407..a35c12e66c7cb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -89,11 +89,9 @@ define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) {
; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v11, (a0)
-; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: li a0, 8
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -125,9 +123,7 @@ define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) {
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vmul.vx v10, v9, a0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 5
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
@@ -197,11 +193,9 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vle16.v v21, (a0)
-; RV32-NEXT: vrgatherei16.vv v16, v8, v21
; RV32-NEXT: li a0, 164
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV32-NEXT: vrgatherei16.vv v16, v8, v21
; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret
@@ -218,11 +212,9 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV64-NEXT: vle64.v v24, (a0)
-; RV64-NEXT: vrgather.vv v16, v8, v24
; RV64-NEXT: li a0, 164
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vrgather.vv v16, v8, v24
; RV64-NEXT: vrgather.vv v16, v12, v20, v0.t
; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: ret
@@ -238,15 +230,13 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv.v.i v20, -1
-; RV32-NEXT: vrgatherei16.vv v12, v20, v16
-; RV32-NEXT: li a0, 113
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle16.v v16, (a0)
-; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
+; RV32-NEXT: vle16.v v17, (a0)
+; RV32-NEXT: li a0, 113
+; RV32-NEXT: vmv.s.x v0, a0
+; RV32-NEXT: vrgatherei16.vv v12, v20, v16
+; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
@@ -275,13 +265,11 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vrgatherei16.vv v12, v8, v16
-; RV32-NEXT: li a0, 140
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle16.v v8, (a0)
+; RV32-NEXT: li a0, 140
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vmv.v.i v16, 5
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
@@ -459,7 +447,6 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: li a0, 70
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
index a883f16877c4b..d5447f09c2082 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
@@ -710,7 +710,6 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
; LMULMAX2-RV32-NEXT: addi a0, a0, 32
; LMULMAX2-RV32-NEXT: vle64.v v14, (a0)
; LMULMAX2-RV32-NEXT: li a0, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a0
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.x v16, a2
@@ -732,7 +731,7 @@ define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
; LMULMAX1-RV32-LABEL: vadd_vx_v16i64:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi a4, a0, 96
-; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
+; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vle64.v v8, (a4)
; LMULMAX1-RV32-NEXT: addi a4, a0, 112
; LMULMAX1-RV32-NEXT: vle64.v v9, (a4)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index 3df3b8c306a77..c6f6d28faf635 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -946,9 +946,7 @@ define void @mulhu_v8i16(<8 x i16>* %x) {
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: li a1, 33
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v10, 3
; CHECK-NEXT: vmerge.vim v10, v10, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu
@@ -1108,11 +1106,9 @@ define void @mulhs_v8i16(<8 x i16>* %x) {
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: li a1, 105
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, 5
; RV32-NEXT: addi a1, a1, -1755
-; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vmv.v.x v9, a1
; RV32-NEXT: lui a1, 1048571
; RV32-NEXT: addi a1, a1, 1755
@@ -1129,11 +1125,9 @@ define void @mulhs_v8i16(<8 x i16>* %x) {
; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: li a1, 105
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: lui a1, 5
; RV64-NEXT: addiw a1, a1, -1755
-; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-NEXT: vmv.v.x v9, a1
; RV64-NEXT: lui a1, 1048571
; RV64-NEXT: addiw a1, a1, 1755
@@ -1156,11 +1150,9 @@ define void @mulhs_v4i32(<4 x i32>* %x) {
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: li a1, 5
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: lui a1, 419430
; RV32-NEXT: addi a1, a1, 1639
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.v.x v9, a1
; RV32-NEXT: lui a1, 629146
; RV32-NEXT: addi a1, a1, -1639
@@ -1214,8 +1206,8 @@ define void @mulhs_v2i64(<2 x i64>* %x) {
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vmadd.vv v10, v8, v9
; RV32-NEXT: li a1, 1
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.s.x v8, a1
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
; RV32-NEXT: vslideup.vi v9, v8, 2
@@ -4179,9 +4171,7 @@ define void @mulhu_v8i32(<8 x i32>* %x) {
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: li a1, 68
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a1
-; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: lui a1, %hi(.LCPI131_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI131_0)
; LMULMAX2-NEXT: vle32.v v10, (a1)
@@ -4193,9 +4183,7 @@ define void @mulhu_v8i32(<8 x i32>* %x) {
; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-NEXT: li a1, 136
-; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.s.x v0, a1
-; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vmv.v.i v10, 2
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
@@ -4270,8 +4258,8 @@ define void @mulhu_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 524288
-; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v12, a1
+; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu
; LMULMAX2-RV32-NEXT: vslideup.vi v14, v12, 5
@@ -4515,9 +4503,7 @@ define void @mulhs_v16i16(<16 x i16>* %x) {
; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vle16.v v9, (a1)
; LMULMAX1-NEXT: li a2, 105
-; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.s.x v0, a2
-; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 7
; LMULMAX1-NEXT: vmerge.vim v10, v10, -7, v0
; LMULMAX1-NEXT: vdiv.vv v9, v9, v10
@@ -4537,11 +4523,9 @@ define void @mulhs_v8i32(<8 x i32>* %x) {
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: li a1, 85
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 419430
; LMULMAX2-RV32-NEXT: addi a1, a1, 1639
-; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32-NEXT: lui a1, 629146
; LMULMAX2-RV32-NEXT: addi a1, a1, -1639
@@ -4576,11 +4560,9 @@ define void @mulhs_v8i32(<8 x i32>* %x) {
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: li a2, 5
-; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2
; LMULMAX1-RV32-NEXT: lui a2, 419430
; LMULMAX1-RV32-NEXT: addi a2, a2, 1639
-; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX1-RV32-NEXT: lui a2, 629146
; LMULMAX1-RV32-NEXT: addi a2, a2, -1639
@@ -4626,7 +4608,6 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32-NEXT: li a1, 17
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 349525
; LMULMAX2-RV32-NEXT: addi a2, a1, 1365
@@ -4637,7 +4618,6 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmulh.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: li a1, 51
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.i v12, -1
@@ -4647,7 +4627,6 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV32-NEXT: li a1, 63
; LMULMAX2-RV32-NEXT: vsrl.vx v8, v12, a1
; LMULMAX2-RV32-NEXT: li a1, 68
-; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0
@@ -4661,27 +4640,25 @@ define void @mulhs_v4i64(<4 x i64>* %x) {
; LMULMAX2-RV64-LABEL: mulhs_v4i64:
; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: li a1, 5
-; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX2-RV64-NEXT: vmv.s.x v0, a1
-; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI136_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI136_0)
-; LMULMAX2-RV64-NEXT: vlse64.v v10, (a1), zero
+; LMULMAX2-RV64-NEXT: vlse64.v v8, (a1), zero
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI136_1)
; LMULMAX2-RV64-NEXT: ld a1, %lo(.LCPI136_1)(a1)
+; LMULMAX2-RV64-NEXT: vle64.v v10, (a0)
; LMULMAX2-RV64-NEXT: vmv.v.i v12, -1
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 0, v0
-; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a1, v0
-; LMULMAX2-RV64-NEXT: vmulh.vv v10, v8, v10
-; LMULMAX2-RV64-NEXT: vmacc.vv v10, v8, v12
+; LMULMAX2-RV64-NEXT: vmerge.vxm v8, v8, a1, v0
+; LMULMAX2-RV64-NEXT: vmulh.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vmacc.vv v8, v10, v12
; LMULMAX2-RV64-NEXT: li a1, 63
-; LMULMAX2-RV64-NEXT: vsrl.vx v8, v10, a1
+; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 1
; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 0, v0
-; LMULMAX2-RV64-NEXT: vsra.vv v10, v10, v12
-; LMULMAX2-RV64-NEXT: vadd.vv v8, v10, v8
+; LMULMAX2-RV64-NEXT: vsra.vv v8, v8, v12
+; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 1afba9254f436..60817765e1d10 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -794,12 +794,10 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX4-NEXT: lui a0, 945060
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32-LMULMAX4-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX4-NEXT: lui a0, 551776
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
-; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-LMULMAX4-NEXT: vslideup.vi v8, v9, 1
; RV32-LMULMAX4-NEXT: ret
;
@@ -827,13 +825,11 @@ define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX8-NEXT: lui a0, 551776
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
-; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 3, e32, m1, tu, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 2
; RV32-LMULMAX8-NEXT: lui a0, 945060
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
-; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index 9c4729b65e449..ca94ba2834a60 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -85,9 +85,8 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV32-NEXT: lbu a0, 0(a0)
; RV32-NEXT: slli a1, a1, 8
; RV32-NEXT: or a0, a1, a0
-; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v8, a0
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, tu, mu
; RV32-NEXT: vslideup.vi v9, v8, 1
; RV32-NEXT: .LBB4_4: # %else2
; RV32-NEXT: vmv1r.v v8, v9
@@ -132,9 +131,8 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV64-NEXT: lbu a0, 0(a0)
; RV64-NEXT: slli a1, a1, 8
; RV64-NEXT: or a0, a1, a0
-; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v8, a0
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
+; RV64-NEXT: vsetivli zero, 2, e16, mf4, tu, mu
; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: .LBB4_4: # %else2
; RV64-NEXT: vmv1r.v v8, v9
diff --git a/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll b/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
index dc2bbe8bfbb25..88a2c81a38bbd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
@@ -16,7 +16,7 @@ define i64 @test(<vscale x 1 x i64> %0) nounwind {
; CHECK-NEXT: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
- ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6
+ ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6 /* e64 */
; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a)
; CHECK-NEXT: $x10 = COPY [[LD]]
; CHECK-NEXT: PseudoRET implicit $x10
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