[PATCH] D127354: Allow bitwidth difference when checking for isOneOrOneSplat.

[Adrian Tong via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG55311801f06d: Allow bitwidth difference when checking for isOneOrOneSplat. (authored by adriantong1024).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127354/new/

https://reviews.llvm.org/D127354

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/add-negative.ll
  llvm/test/CodeGen/AArch64/minmax.ll


Index: llvm/test/CodeGen/AArch64/minmax.ll
===================================================================
--- llvm/test/CodeGen/AArch64/minmax.ll
+++ llvm/test/CodeGen/AArch64/minmax.ll
@@ -123,10 +123,8 @@
 ; CHECK-LABEL: t12:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmhi v2.16b, v1.16b, v0.16b
-; CHECK-NEXT:    movi v3.16b, #1
 ; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
-; CHECK-NEXT:    and v1.16b, v2.16b, v3.16b
-; CHECK-NEXT:    add v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    sub v0.16b, v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %t1 = icmp ugt <16 x i8> %b, %a
   %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
Index: llvm/test/CodeGen/AArch64/add-negative.ll
===================================================================
--- llvm/test/CodeGen/AArch64/add-negative.ll
+++ llvm/test/CodeGen/AArch64/add-negative.ll
@@ -1,17 +1,14 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
-; FIXME: D127354
 define <8 x i16> @add_to_sub(<8 x i16> %0, <8 x i16> %1) {
 ; CHECK-LABEL: add_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    movi v3.8h, #1
 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT:    cmhi v1.8h, v2.8h, v1.8h
 ; CHECK-NEXT:    cmhi v0.8h, v2.8h, v0.8h
-; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
-; CHECK-NEXT:    add v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    cmhi v1.8h, v2.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
   %3 = icmp ult <8 x i16> %0, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
   %4 = sext <8 x i1> %3 to <8 x i16>
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10666,10 +10666,9 @@
 }
 
 bool llvm::isOneOrOneSplat(SDValue N, bool AllowUndefs) {
-  // TODO: may want to use peekThroughBitcast() here.
-  unsigned BitWidth = N.getScalarValueSizeInBits();
-  ConstantSDNode *C = isConstOrConstSplat(N, AllowUndefs);
-  return C && C->isOne() && C->getValueSizeInBits(0) == BitWidth;
+  ConstantSDNode *C =
+      isConstOrConstSplat(N, AllowUndefs, /*AllowTruncation*/ true);
+  return C && C->isOne();
 }
 
 bool llvm::isAllOnesOrAllOnesSplat(SDValue N, bool AllowUndefs) {


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