[llvm] 5531180 - Allow bitwidth difference when checking for isOneOrOneSplat.
Adrian Tong via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 16 09:04:52 PDT 2022
Author: Adrian Tong
Date: 2022-06-16T16:04:20Z
New Revision: 55311801f06d33a71deae80209dd5640d5e7463e
URL: https://github.com/llvm/llvm-project/commit/55311801f06d33a71deae80209dd5640d5e7463e
DIFF: https://github.com/llvm/llvm-project/commit/55311801f06d33a71deae80209dd5640d5e7463e.diff
LOG: Allow bitwidth difference when checking for isOneOrOneSplat.
This helps handling a case where the BUILD_VECTOR has i16 element type
and i32 constant operands
t2: v8i16 = setcc t8, t17, setult:ch
t3: v8i16 = BUILD_VECTOR Constant:i32<1>, ...
t4: v8i16 = and t2, t3
t5: v8i16 = add t8, t4
This can be turned into t5: v8i16 = sub t8, t2, and allows us to remove
t3 and t4 from the DAG.
Differential Revision: https://reviews.llvm.org/D127354
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/add-negative.ll
llvm/test/CodeGen/AArch64/minmax.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index bf222a77cbcc8..598f0c5f1247f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10666,10 +10666,9 @@ bool llvm::isNullOrNullSplat(SDValue N, bool AllowUndefs) {
}
bool llvm::isOneOrOneSplat(SDValue N, bool AllowUndefs) {
- // TODO: may want to use peekThroughBitcast() here.
- unsigned BitWidth = N.getScalarValueSizeInBits();
- ConstantSDNode *C = isConstOrConstSplat(N, AllowUndefs);
- return C && C->isOne() && C->getValueSizeInBits(0) == BitWidth;
+ ConstantSDNode *C =
+ isConstOrConstSplat(N, AllowUndefs, /*AllowTruncation*/ true);
+ return C && C->isOne();
}
bool llvm::isAllOnesOrAllOnesSplat(SDValue N, bool AllowUndefs) {
diff --git a/llvm/test/CodeGen/AArch64/add-negative.ll b/llvm/test/CodeGen/AArch64/add-negative.ll
index e62c3e421a477..ec24d2187b75e 100644
--- a/llvm/test/CodeGen/AArch64/add-negative.ll
+++ b/llvm/test/CodeGen/AArch64/add-negative.ll
@@ -1,17 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
-; FIXME: D127354
define <8 x i16> @add_to_sub(<8 x i16> %0, <8 x i16> %1) {
; CHECK-LABEL: add_to_sub:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: movi v3.8h, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
-; CHECK-NEXT: cmhi v1.8h, v2.8h, v1.8h
; CHECK-NEXT: cmhi v0.8h, v2.8h, v0.8h
-; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
-; CHECK-NEXT: add v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: cmhi v1.8h, v2.8h, v1.8h
+; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%3 = icmp ult <8 x i16> %0, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
%4 = sext <8 x i1> %3 to <8 x i16>
diff --git a/llvm/test/CodeGen/AArch64/minmax.ll b/llvm/test/CodeGen/AArch64/minmax.ll
index 59faf0efc35dd..be9f45e6eea44 100644
--- a/llvm/test/CodeGen/AArch64/minmax.ll
+++ b/llvm/test/CodeGen/AArch64/minmax.ll
@@ -123,10 +123,8 @@ define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: t12:
; CHECK: // %bb.0:
; CHECK-NEXT: cmhi v2.16b, v1.16b, v0.16b
-; CHECK-NEXT: movi v3.16b, #1
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: add v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%t1 = icmp ugt <16 x i8> %b, %a
%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
More information about the llvm-commits
mailing list