[PATCH] D127858: [RISCV] Turn on SeparateConstOffsetFromGEPPass for RISC-V target
Elena Lepilkina via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 16 03:47:50 PDT 2022
eklepilkina added a comment.
Now clang for RISC-V doesn't use offset addressing in generated assembly. Example from Dhrystone
addiw a0, s1, 5
slli a1, a0, 0x2
add a2, s4, a1
sw s2, 0(a2)
addiw a3, s1, 6
slli a3, a3, 0x2
add a3, a3, s4
sw s2, 0(a3)
addiw a3, s1, 35
slli a3, a3, 0x2
add a3, a3, s4
sw a0, 0(a3)
It's inefficient because we can use offsets.
Adding this pass allows to generate the next code
addiw a4, a2, 5
slli a5, a2, 2
add a0, a0, a5
sw a3, 20(a0)
sw a3, 24(a0)
sw a4, 140(a0)
...
SeparateConstOffsetFromGEPPass is used to solve this problem in targets with limited addressing modes.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D127858/new/
https://reviews.llvm.org/D127858
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