[PATCH] D127939: [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:5280
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
-  assert(NOutVT.isVector() && "Type must be promoted to a vector type");
+  assert(NOutVT.isScalableVector() &&
+         "Type must be promoted to a scalable vector type");
----------------
frasercrmck wrote:
> Jimerlife wrote:
> > david-arm wrote:
> > > Jimerlife wrote:
> > > > craig.topper wrote:
> > > > > Why this change? llvm.stepvector intrinsic works for fixed vectors.
> > > > Yes, llvm.stepvector intrinsic works for fixed vectors, but ISD::STEP_VECTOR is only work for scalable vector. I'm not sure my understanding is right?
> > > I agree with @craig.topper. I don't understand why we're changing the assert here. This should work for fixed vectors too so we should be asserting that the result is a vector, i.e. either fixed-width or scalable.
> > If call `<vscale x 4 x i15> @llvm.experimental.stepvector.nxv4i15()`, it generated `nxv4i15 = step_vector` node. 
> > But if call `<4 x i15> @llvm.experimental.stepvector.v4i15()`, it generated `v4i15 = build_vector` node.
> > 
> > My understand is that fixed vectors cann't generate node like `v4i15 = step_vector`.
> > So, only scalable vector will go through PromoteIntRes_STEP_VECTOR if it need to promote.
> > This is right? @craig.topper  @david-arm
> That's my understanding, yes - we don't generate `ISD::STEP_VECTOR` for fixed-length vector types. Take a look at `SelectionDAG::getStepVector`'s implementation. I assume that's done for canonicalization purposes.
My apologies @Jimerlife, you are absolutely right! I was thinking about the SelectionDAG::getStepVector interface, but this only returns STEP_VECTOR for scalable vectors. In fact, the ISD node states:

  /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
  /// of a linear sequence of unsigned values starting from 0 with a step of
  /// IMM, where IMM must be a TargetConstant with type equal to the vector
  /// element type. The arithmetic is performed modulo the bitwidth of the
  /// element.
  ///
  /// The operation does not support returning fixed-width vectors or
  /// non-constant operands.
  STEP_VECTOR,


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https://reviews.llvm.org/D127939