[PATCH] D111029: [X86] Prefer 512-bit vectors on Ice Lake Server cpus (PR48336)

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 16 02:42:43 PDT 2022


RKSimon updated this revision to Diff 437481.
RKSimon retitled this revision from "[X86] Prefer 512-bit vectors on Ice/Rocket/TigerLake (PR48336)" to "[X86] Prefer 512-bit vectors on Ice Lake Server cpus (PR48336)".
RKSimon edited the summary of this revision.
RKSimon added a comment.

Updated to just target Ice Lake Server


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111029/new/

https://reviews.llvm.org/D111029

Files:
  llvm/lib/Target/X86/X86.td
  llvm/test/CodeGen/X86/min-legal-vector-width.ll

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