[PATCH] D127939: [LegalizeTypes][RISCV][NFC] Modify assert in PromoteIntRes_STEP_VECTOR and add some tests for RISCV

[WangLian via Phabricator via llvm-commits]

Jimerlife added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll:318
 
-define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:
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craig.topper wrote:
> The rest of this patch involve stepvector, but this doesn't. Unless I'm missing something this should be a different patch.
Removed this change.


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  https://reviews.llvm.org/D127939/new/

https://reviews.llvm.org/D127939