[llvm] 70f2bef - [LoongArch] Use register R0 (ZERO) for constant 0

Weining Lu via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 15 22:44:44 PDT 2022


Author: Weining Lu
Date: 2022-06-16T13:43:11+08:00
New Revision: 70f2befaf7ad60b8bae62f01f89dfd8bdb890234

URL: https://github.com/llvm/llvm-project/commit/70f2befaf7ad60b8bae62f01f89dfd8bdb890234
DIFF: https://github.com/llvm/llvm-project/commit/70f2befaf7ad60b8bae62f01f89dfd8bdb890234.diff

LOG: [LoongArch] Use register R0 (ZERO) for constant 0

Differential Revision: https://reviews.llvm.org/D127205

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
    llvm/test/CodeGen/LoongArch/imm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
index 13d7218d36419..2e5b3ead40d3e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -37,9 +37,14 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) {
     break;
   case ISD::Constant: {
     int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+    if (Imm == 0 && Node->getSimpleValueType(0) == GRLenVT) {
+      SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
+                                           LoongArch::R0, GRLenVT);
+      ReplaceNode(Node, New.getNode());
+      return;
+    }
     SDNode *Result = nullptr;
     SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
-
     // The instructions in the sequence are handled here.
     for (LoongArchMatInt::Inst &Inst : LoongArchMatInt::generateInstSeq(Imm)) {
       SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, GRLenVT);

diff  --git a/llvm/test/CodeGen/LoongArch/imm.ll b/llvm/test/CodeGen/LoongArch/imm.ll
index 3d6cfce3dabcc..fb0dcf21f231e 100644
--- a/llvm/test/CodeGen/LoongArch/imm.ll
+++ b/llvm/test/CodeGen/LoongArch/imm.ll
@@ -1,5 +1,13 @@
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+define i64 @imm0() {
+; CHECK-LABEL: imm0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    move $a0, $zero
+; CHECK-NEXT:    jirl $zero, $ra, 0
+  ret i64 0
+}
+
 define i64 @imm7ff0000000000000() {
 ; CHECK-LABEL: imm7ff0000000000000:
 ; CHECK:       # %bb.0:


        


More information about the llvm-commits mailing list