[PATCH] D126807: [PowerPC] Fix LQ-STQ instructions to use correct offset and base

[Kai Luo via Phabricator via llvm-commits]

lkail requested changes to this revision.
lkail added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:496
+    // This is a spill/restore of a quadword.
+    if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) {
+      LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
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This looks redundant. Test cases can pass without this change.


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Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1589
+  // emitting the X-Form pseudo.
+  if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) {
+    assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode");
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Expanding two `PPCCustomInserterPseudo` instructions here looks odd.

I would expect these two instructions expanded after `prologepilog`, in `postrapseudos`. This is making us expand these two instructions twice in backend code. It's more adequate to make them `PPCPostRAExpPseudo` rather than `PPCCustomInserterPseudo`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126807/new/

https://reviews.llvm.org/D126807