[PATCH] D127848: [CodeGen] Fix the bug of machine sink

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added a comment.

Yes that's what I wrote. It seems there is an exception that if for all operands you get `readReg() == false` (that includes undef) then it is indeed allowed to have a VReg without a definition.

In D127848#3585733 <https://reviews.llvm.org/D127848#3585733>, @LuoYuanke wrote:

> In D127848#3585723 <https://reviews.llvm.org/D127848#3585723>, @MatzeB wrote:
>
>> I see this code in the MachineVerifier:
>>
>>   } else if (MRI->def_empty(Reg)) {
>>     report("Reading virtual register without a def", MO, MONum);
>>
>> Which reads to me that we do not allow virtual registers without a definition if there is at least 1 read of the register. But I guess that means you can indeed have a vreg without a def if all the uses are marked `undef` or are debug operands or similar situations where `MO.readsReg()` is false.
>
> We can add undef flag to tell verifier it is undef register, e.g., `%2:gr32 = MOV32rr undef %3:gr32`.




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https://reviews.llvm.org/D127848