[llvm] 16547f9 - [CodeGen] Fix the bug of machine sink

[via llvm-commits]

Author: Luo, Yuanke
Date: 2022-06-15T23:35:52+08:00
New Revision: 16547f9fbbd56c7b8256b6eea1ccd8b1547ef4e5

URL: https://github.com/llvm/llvm-project/commit/16547f9fbbd56c7b8256b6eea1ccd8b1547ef4e5
DIFF: https://github.com/llvm/llvm-project/commit/16547f9fbbd56c7b8256b6eea1ccd8b1547ef4e5.diff

LOG: [CodeGen] Fix the bug of machine sink

The use operand may be undefined. In that case we can just continue to
check the next operand since it won't increase register pressure.

Differential Revision: https://reviews.llvm.org/D127848

Added: 
    llvm/test/CodeGen/X86/sink-down-undef-use.mir

Modified: 
    llvm/lib/CodeGen/MachineSink.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 797433e7a280..96d575ffb3fc 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -823,6 +823,8 @@ bool MachineSinking::isProfitableToSinkTo(Register Reg, MachineInstr &MI,
         return false;
     } else {
       MachineInstr *DefMI = MRI->getVRegDef(Reg);
+      if (!DefMI)
+        continue;
       MachineCycle *Cycle = CI->getCycle(DefMI->getParent());
       // DefMI is defined outside of cycle. There should be no live range
       // impact for this operand. Defination outside of cycle means:

diff  --git a/llvm/test/CodeGen/X86/sink-down-undef-use.mir b/llvm/test/CodeGen/X86/sink-down-undef-use.mir
new file mode 100644
index 000000000000..7f14cecbc311
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sink-down-undef-use.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-- -run-pass=machine-sink -o - %s | FileCheck %s
+
+---
+name:            foo
+alignment:       16
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gr32 }
+  - { id: 1, class: gr32 }
+  - { id: 2, class: gr32 }
+  - { id: 3, class: gr32 }
+frameInfo:
+  maxAlignment:    4
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT:   liveins: $edi, $esi
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   JMP_1 %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr undef %1:gr32
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32rr1:%[0-9]+]]:gr32 = MOV32rr undef %3:gr32
+  ; CHECK-NEXT:   JCC_1 %bb.1, 15, implicit undef $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   MOV32mr $rip, 1, $noreg, 12, $noreg, [[MOV32rr1]]
+  ; CHECK-NEXT:   JCC_1 %bb.3, 15, implicit undef $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   RET 0, undef $eax
+  bb.0.entry:
+    liveins: $edi, $esi
+    JMP_1 %bb.2
+  bb.1:
+    %0:gr32 = MOV32rr undef %1:gr32
+  bb.2:
+    %2:gr32 = MOV32rr undef %3:gr32
+    JCC_1 %bb.1, 15, undef implicit $eflags
+    JMP_1 %bb.3
+
+  bb.3:
+    MOV32mr $rip, 1, $noreg, 12, $noreg, %2
+    JCC_1 %bb.3, 15, undef implicit $eflags
+    JMP_1 %bb.4
+
+  bb.4:
+    RET 0, undef $eax
+
+...