[PATCH] D127843: [AArch64][SME] Add the zero intrinsic

[David Sherwood via Phabricator via llvm-commits]

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The SME zero instruction takes a mask as an input declaring which
64-bit element tiles should be zeroed. There is a 1:1 mapping
between the zero intrinsic and the instruction, however we also
want to make the register allocator aware that some tile
registers are being written to.

We can actually just use the custom inserter for a pseudo instruction
to correctly mark all the appropriate registers in the mask as
implicitly defined by the operation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127843

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/CodeGen/AArch64/sme-intrinsics-zero.ll

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