[PATCH] D127642: [RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.

[Kito Cheng via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
kito-cheng marked an inline comment as done.
Closed by commit rG687e56614fa0: [RISCV] Fixing undefined physical register issue when subreg liveness tracking… (authored by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127642/new/

https://reviews.llvm.org/D127642

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir


Index: llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -O2 -mtriple riscv64 -riscv-enable-subreg-liveness \
+# RUN:     -verify-machineinstrs -run-pass=riscv-expand-pseudo -o - 2>&1 \
+# RUN:     | FileCheck %s
+--- |
+  define void @foo() #0 {
+  entry:
+    ret void
+  }
+...
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true }
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $x10, $x11
+    ; CHECK-LABEL: name: foo
+    ; CHECK: liveins: $v8m2, $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: VS2R_V $v8m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK-NEXT: $x10 = ADD $x10, $x11
+    ; CHECK-NEXT: VS2R_V $v10m2, $x10, implicit $v8m2_v10m2 :: (store unknown-size into %stack.0, align 8)
+    ; CHECK-NEXT: PseudoRET
+    PseudoVSPILL2_M2 killed $v8m2_v10m2, killed $x10, killed $x11 :: (store unknown-size into %stack.0, align 8)
+    PseudoRET
+
+...
Index: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -314,10 +314,15 @@
     assert(LMUL == 1 && "LMUL must be 1, 2, or 4.");
 
   for (unsigned I = 0; I < NF; ++I) {
+    // Adding implicit-use of super register to describe we are using part of
+    // super register, that prevents machine verifier complaining when part of
+    // subreg is undef, see comment in MachineVerifier::checkLiveness for more
+    // detail.
     BuildMI(MBB, MBBI, DL, TII->get(Opcode))
         .addReg(TRI->getSubReg(SrcReg, SubRegIdx + I))
         .addReg(Base)
-        .addMemOperand(*(MBBI->memoperands_begin()));
+        .addMemOperand(*(MBBI->memoperands_begin()))
+        .addReg(SrcReg, RegState::Implicit);
     if (I != NF - 1)
       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
           .addReg(Base)


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