[PATCH] D127664: [AMDGPU] gfx11 ldsdir intrinsics and ISel

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:1465
+  Intrinsic<[llvm_float_ty],
+            [llvm_i32_ty],
+            [IntrReadMem, IntrSpeculatable, IntrWillReturn]>;
----------------
critson wrote:
> arsenm wrote:
> > Also would expect this to be an addrspace 3 pointer
> This is setting M0, the same as parameter loads.
> Construction of M0 values is handled by the front-end because it is not a pure address pointer but rather a combination of address offset and flags describing the data type.
> I guess we could rework this to form M0 in the backend based on an address 3 pointer and a return type.
I think it makes sense to have an intrinsic that closely corresponds to the instruction itself. Maybe add a comment explaining this fact about M0?

I agree with Matt that the return value should be mangled.


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https://reviews.llvm.org/D127664